# Vectorless methods for deriving instantaneous current

 Summary: Using simulation to derive peak currents has bee described elsewhere on this site. This article describes the various vectorless methods that are used for obtaining instantaneous currents, focussing on the techniques before briefly describing how static timing analysis and timed ATPG approaches provide efficient solutions.

Now we come to vectorless methods of calculating peak voltage drop. I hesitate to use the word dynamic here, as these methods do not calculate a time-varying profile of the VDD/VSS networks’ branch currents or node voltages; instead, the objective here is that for each VDD/VSS net sub-node this analysis computes an upper-bound on the instantaneous current; that is, for each VDD (and/or VSS) power supply sub-node, what is the greatest current draw experienced during circuit operation. The ‘instant’ referred to in the word ‘instantaneous’ refers to a small time interval, equal to or shorter than the fastest signal transition.

Note that this analysis gives current draw only, from which voltage drop may be derived. To determine performance variation under the influence of this voltage drop requires additional work. You could go to the effort of annotating the worst voltage drop at every component and run performance verification, but as described in an earlier article, you’ll end up with an extraordinary conservative worst-case, unlikely ever to be seen in chip operation. In addition, this conservatism leads to over-design - too much metal, on too many layers, dedicated to power routing. And with each additional layer adding about 10% to the die cost, some high-volume consumer designs may become economically unfeasible.

Instantaneous analysis

Imagine yourself in the middle of a typical synthesized circuit. All around you is activity, both topologically and temporally diffuse - that is, distributed in both time and location. Somehow we have to make sense of this seemingly semi-random activity, and to determine how the current is accumulated and distributed around the circuit. The good news is that we can use characteristics of the circuit to our advantage in performing an analysis to estimate, without running dynamic simulation at any level of abstraction, the instantaneous peak current draw.

How so? Well, it’s long been known, and it’s easy enough to verify, that the peak current draw in a circuit is coincident with or immediately after the active edge of the clock signal source - as the clock buffers distributed though the clock net - both global and local - switch state, and the register elements themselves also flip state. Because our objective is peak current draw we can and should assume that a) all clock gating cells are in pass-through mode, and b) all registers will change state.

Note that no state information is required for this analysis. If we want to complicate the analysis, trading off some additional computation for the sake of increased precision, we can determine topology or state-transferrence that would prevent downstream registers from switching (for instance, in back-to-back registers, the second register will switch in the clock cycle after the first one has switched.) To further complicate the register clocking-focussed analysis, pseudo-states (defined here as levels of inversion) can be propagated along cells in the clock path, and used to further refine the population of register elements that change state.

Now consider the combinatorial elements in the signal paths. Circuit activity propagates from register to register, along logic cones, initiated by the active edge of the clock signal. Some gates will pass signals, others will block them. In general, those gates earlier in the timing path, nearer the register outputs, contribute a greater amount to the current draw than do those gates further away. In the same spirit as described above for combinatorial cells in the clock path, analysis of states or inversion levels can be used to refine the potential activity and current waveform at each of the gates or cells in the logic cone.

With these clock and cone analyses being performed after the circuit has been levelized, currents are then accumulated and the peak current draw for the entire circuit can be determined. If placement information is available to the tool, regional activity at a chosen level of granularity can be determined.

These time-based current waveforms can then be output from our newly-developed tool as piecewise linear or piecewise constant current sources, and attached to the extracted power grid model (described in a previous article) to that peak voltage drop can be determined. Post-processing in the form of filtering, sorting, and bucketing can give users a text-based report of worst voltage drop nodes. With additional work, data can be back-annotated to a schematic or layout view in order to provide the layout engineer with additional information so that layout can be improved, perhaps by widening or adding metal, or by adding or relocating decaps.

Methods based on static timing analysis

The arrival time, duration and edge sense of switching events as they impinge on all cells in the synthesized design can be obtained from any static timing analysis tool. Post-processing this output report for use as input to the computation flow described in the section above short-cuts a lot of the analysis steps described. The expense, of course, is the interruption of static-timing analysis, and post-processing a few gigabytes of report file. Building this analysis into STA, though, reduces much inefficiencies.

Methods based on timed ATPG

Timed ATPG is a generalization of the more usual ATPG problem. Where regular ATPG aims to distinguish between a fault and a fault-free circuit, and to provide a vector that demonstrates that difference, timed ATPG finds an input vector that satisfies both functional and timing behaviour. PODEM-based timed ATPG has been criticised for sluggish performance when analyzing large circuits, driving much work on pre-characterising intermediate analyses, resulting in superior run times. With timed ATPG, the maximum instantaneous current through supply lines can be calculated (see the Krstic and Cheng paper from DAC97.)