In the previous article we reviewed static IR voltage drop, where a constant-current source is attached to some or all of the end or intermediate nodes of an extracted power net. In effect, this approach models the situation in the diagram below. Note that this diagram shows only a small subset of power net nodes have sources attached; in practice, the majority if not all of the lowest level nodes will sink current.

In this article we’re going to describe replacing the constant-current sources, annotating instead time-varying piecewise-constant current sources. The locations, or tap points, to which these sources are attached is as before, namely either at the lowest or intermediate nodes in the power net. The diagram below shows the approach this methodology takes.

Much of this article describes alternative methods of calculating the value of these piecewise-constant current sources, and the approaches used to determine the granularity in the time domain.

Calculating these abstracted time-varying currents can be done in several ways, generally falling into one of the following two most common methods:

• Vector-dependent, or simulation-driven, methods
• Vectorless methods, usually static-timing driven (the subject of tomorrow’s article)

Vector-dependent methods

Like all simulation-driven verification, whether RTL, gate or transistor-level, these methods are extraordinarily computationally intensive. There are methodologies that employ RTL simulation to discern discrete time periods of most significant circuit activity, and use these periods, cut out with appropriate initialization sequences, as stimulus to drive the voltage drop analysis, and these do help to reduce the burden somewhat.

Abstracting information from simulation, through SAIF or verbose VCD files, is possible, as is the option to vary the time-granularity of the current sources through averaging segments. In figure 2 above, 5 segments are shown. The compute effort could be reduced by averaging segments 1 and 2, and segments 3 and 4. The cost would be to precision. Averaging across the entire time interval would give good average currents for current-density analysis, or for static voltage drop analysis (as in figure 1 above.)

Given a switching interval (or its inverse, frequency), it is possible to calculate the current for each node, for each time interval, using the equation I = 0.5 * effective_load_capacitance * VDD^2 * effective_frequency. These are the values plugged into the index tables of the piecewise current model.

One of the most-repeated complaints about all vector-driven methods is that it is difficult to find the vector pairs or patterns that maximally draw current from the power grid, and that using user-defined patterns tends to underestimate the voltage drop and failing to identify all potential problem areas. There’s an element of truth in this argument, and I am in broad agreement with it. For gate-level circuits, a successful approach to identify such vector pairs has been developed using a multi-objective genetic algorithm (see Yi-Min Jiang’s paper in ISLPED99.) This approach, though, like all two-step approaches (which in step one compute currents and in an independent step two compute their accumulation and distribution within the power grid) abstract away some critical information. We’ll return to this in a later article, when we discuss in detail the two-step approaches and their limitations.

In the next article we’ll discuss the vectorless methods.

Those of you who know me well also know that I am liable to get a little bit cranky from time to time (I used to think it was my age, but it’s not getting any better as I wait for the AARP cards to come through the mail.) One of the things that most wraps me around the axle is EDA marketeers being economical with the truth, and misleading designers either by omission or by a lack of real, hard-won experience.

So it was with reddening cheeks and mounting blood pressure that I read on SCDsource (the redoubtable Richard Goering serving as editor-in-chief) an “In My Opinion” piece written by Paul Estrada of Berkeley Design Automation and entitled “Don’t compromise on true SPICE accuracy.” The thrust of this piece is that accuracy of simulation is critically important and the evidence given to support the main assertions is this:

…we ran a true Spice accurate simulator on a production analog-to-digital converter (ADC) with a relative tolerance (RelTol) of 1e-3 (Spice default), and then repeated the run with a RelTol of 1e-2 (a greatly relaxed tolerance) to approximate 0.1% inaccuracy and 1% inaccuracy respectively.

Pi, on this you’re wrong. Or you’re gargling bong water.

RELTOL is the ratio between the numerical answers computed for the current and previous iterations. We users usually increase it a little if we want to improve DC convergence, but there’s a balance - setting it too high gives us the SPICE equivalent of the blue screen, the “timestep too small” error. There’s an explanation of how RELTOL affects convergence in note 3 of an AllAboutEDA SPICE article. But that’s all RELTOL is, a method of controlling what delta voltage value across iterations causes “convergence”; it has nothing to do with simulation accuracy. It affects local truncation error, which in turn affects numerical noise, but using it as a method of controlling simulation accuracy is bad.

And here’s the thing. I’ve been saying my whole working life in semiconductor or EDA that EDA tools are just that: tools. We can use them crudely, like trying to craft a finely-fitted dovetail joint with an axe. Or we can become craftsmen, serving time as an apprentice and learning how to use the tools with power, refinement and elegance. Changing RELTOL and asserting it changes the simulation accuracy (or precision) is an elementary error, and one that jars particularly because one of the main selling points of Berkeley’s Analog FastSPICE is its elegant convergence.

Nascentric have just announced a hardware-accelerated version of their OmegaSim SPICE that offloads the computationally-expensive transistor evaluations from the main CPU(s) and onto an nVidia PCIe card holding a single GPU containing 128 multi-threaded processors.

This is an intriguing approach - using off-the-shelf acceleration hardware hasn’t been something the EDA industry has taken to, preferring instead to design and make their own (see hardware accelerators, emulators, and other attempts passim.) We’ve predicted here the move to distributed computing, multi-core and multi-threading, and OmegaSim GX is part of that move. Accelerating MOS evaluation is a great first step, and I’d be really interested to see some real, open and transparent benchmarking (something most EDA software licensing expressly prohibits, by the way.)

In addition, the number of MOS evaluations increase hugely in tightly-coupled circuits; fully-extracted post-layout netlists including a large number of fine-granularity coupling capacitors and a full power and ground distribution system create havoc in SPICE and Fast-SPICE alike. I’d be curious to see, as the solve-load ratio changes with increasing coupling, how GX performs.

In the second article in this series we introduced the electrical and physical data made available for each power net. As an abstract description you can consider each power distribution network to be mesh-like, of varying sparsity, with voltage sources from external to the chip connecting at some (peripheral or distributed) locations on higher level metal layers, and with transistor connections made on the lowest or contact layer, usually that immediately beneath metal1.

The primary variation in the capability offered by voltage drop analysis tools is in what gets connected to this power distribution network. On the chip itself there will be a PMOS source at the VDD-connected contact, and an NMOS drain at the GND-connected contact, but in the voltage drop analysis tool, like all EDA tools, there’s going to be a ‘modeled equivalent’ of the transistor. In this article we’re going to introduce the simplest of all possible models, a constant-current source.

A stylized description is given in the following diagram:

The solder bumps at the top-most level connect to a coarse grid. Below this are metal layers that distribute power in various directions:

• x direction; for instance, the power route contained within each standard cell entity, connected by direct abutment to adjacent neighbors.
• y direction; for instance strapping and feed-throughs to connect power from one stick of gates to an adjacent one (perhaps interdigiated).
• both directions; for instance, power rings surrounding embedded cores and memories, with connections to the next higher and next lower levels.

Each intersection, in each layer, has a capacitor connected to ground.

In this stylized description, MOS or gate currents are modeled by a constant-current source. There are several questions designers need to consider when using this approach:

1. How many will there be?

   The number of current sources can be as many as the number of MOS elements attached to the power net. In the case where a large, pre-characterized IP block (core, or memory, for instance) is instantiated, it’s common to take the peak I(VDD) figure, and divide it by the number of expected taps at the power ring/core top-level to get an estimated peak current per tap. In the absence of detailed design information, user may define an expected number of taps, based on prior design experience.

2. What will their value be?

   There are many methods to determine the value of the constant-current source, including:

   • A user-defined estimate, perhaps specified by instance name, die x,y region; or by wildcarding the instance name.
   • Each MOS transistor can be analyzed, and given a user-supplied estimate of the switching frequency (again, possibly modified by die x,y region), the I(max) of the MOS can be calculated as 0.5*load_cap*frequency*VDD^2
   • The I(DSAT) of each MOS can be used, modified by x,y region again.
   • In the example given above, where a pre-characterized RAM or IP block is instantiated, distributing the known peak current, I(MAX) over N taps results in I(MAX)/N per tap.
   • With the clock network alone constituting anywhere from 30% to 70% of a high-performance digital design’s current draw, some detailed analysis of this network, suitably back-annotated with VDD and GND can give a good first-level estimate of expected peak current.
3. Where will they be located?

   The taps will be located at the interface between the power net and the switching entity, typically at the contact layer. For IP blocks and RAMS the interface is, for these static currents, at the power rign of the instantiated block.

4. What kind of analysis is supported?

   At the taps for which current sources have been applied, the voltage VDD’ (equal to VDD - IR) has beeb calculated. This gives us the DC drop for this set of estimated currents, without inductive drop, and without the current contribution made by decoupling caps - in short, this analysis assumes all current will be coming from off-chip, through the power or ground bond pads.

   This is a slightly unreal situation, and since decaps typically provide around one half of the peak current requirements, serving to increase the regulation, the computed VDD’ is not terribly precise.

   So this analysis is limited to roughly checking if the VDD’ varies from nominal VDD by more than the budgetted variance (as well as a quick check of the DC current density though the power net conductors - see a future article). Performance verification under this DC drop value can be undertaken — some attempts have been made, particularly with static timing tools, to take this set of VDD’ values, back-annotate them to the circuit, and recalculate the new critical path timing value — but it gives a result of poor precision that does not necessarily approach the upper bound of variance, because there are no dynamic voltage gradients that would exist on the real chip.

   Also, if all the current taps are peak values, or estimated conservatively, the VDD’ value is going to be extremely conservative.

At best this analysis, using constant-current values of varying degree of precision, can give a very rough idea of the robustness of the power net. Expected results from this analysis should be:

• Does the VDD variation meet budgetted value, within 50% or so?
• Is the DC, unidirectional current density within acceptable limits for the metallization and via designs?
• Are there any gross errors in the power net - things like disjoint net segments, where power has not been connected, or current starving to the MOS because of inordinately high power net resistance (too few vias, or conductors laid out too narrow.)
• Is there too little VDD variation? This could mean that too much metal, in tracks laid down too thick, and on too may metal layers, has been dedicated to the power net. This compromises routing resources for signal nets, and wastes metal layers. At around 5% to 10% of die cost per upper metal layer, it pays to be economical with power routing.

In a recent (Mar 10, 2008) press release, Synopsys announced that the 2008.03 release of HSPICE offers significant performance enhancements. The first area of improvement is for single-processor machines, and while this in itself is useful for designers, with the processor clock speed stalled, or even reducing slightly in an attempt to manage power and thermal issues, these can at best be incremental improvements that users have come to expect over the lifetime of a successful software product such as HSPICE.

The second area is one we at AllAboutEDA find hugely exciting, and a great indicator of better things to come. It’s all part of the just-announced Synopsys plan for multi-core EDA world domination. HSPICE has offered a multi-threaded version for a little while, focussed on pre-layout designs (for a discussion of how SPICE scales with coupled structures, extracted data, etc, see this article.) In the 2008.03 HSPICE release, however, support is extended to fully-extracted post-layout netlists, containing in excess of a million parasitic RC components. Applying an approximate rule-of-thumb, and assuming that this million components includes power and ground nets (something Synopsys haven’t explicitly stated), we’re expecting designs of around the 50k to 100k MOS size to fall into this set.

For analog and mixed-signal (A/MS) components, or large AMS IP blocks verified externally before inclusion in a larger chip context, this is right in the sweet spot. Kudos to Synopsys. It’s going to be very interesting to see how the multi-core circuit simulation providers, such as Magma, Xoomsys and Gemini DA respond to this. We will, of course, keep you posted.

Notes
Improvements are in DC convergence, time-step control, netlist parsing and model performance.

Here a word about quality of results for voltage drop analysis tools specifically, though the same argument can also be applied more generally to all EDA tools.

The extracted power net, containing R and C values of parasitics in the power distribution networks, usually shows close correlation across various extraction tools. This is hardly surprising. As we described in our post on physical data, resistance extraction is performed by fracturing the net segment into smaller, manageable geometries, and then “counting the squares” in each geometry. Applying the law of large numbers here, the intuitive conclusion is that accuracy can be increased by counting more, smaller squares.

For capacitance we have to consider the geometries involved; metal for power distribution is usually fairly wide and not at all like the tall, skinny metal laid down for signal nets. As such, fringing and sidewall capacitance contribute less to the over capacitance value of the power net geometry. Also, power nets are at more or less a fixed constant voltage (there is an AC component superimposed on the DC value, but it’s fairly small), and so the current bled from or into the power net from adjacent signal nets (calculated as I=C.dV/dt) is very small, and ignoring it has negigible effect on accuracy.

So the accuracy of voltage drop analysis, given that extractor A and extractor B are going to come up with very similar extracted RC values, comes down to the quality of the currents modeled. Different tools, at different stages in the design flow, have varying data available to them - some “better” [1] than others.

These currents typically fall into the following groups:

• Static currents
1. Constant-current sources
2. Pseudo-static currents
• Dynamic currents
1. Two-step, or decoupled, analysis
2. Direct-coupled analysis

Each one of these numbered items is the subject of an AllAboutEDA post - if the numbered bullets are hyperlinks, go ahead and click on them to read what we have to say about the current derivation, and the type of voltage drop analysis being performed. In general, the quality of results and the rigor of the analysis performed goes from least to best down the list, but there’s a healthy overlap, especially for the static currents.

Notes
1. What makes a better current? I would posit that it’s the one that has the smaller difference between the modeled current itself and the real design, on silicon, configured in exactly the same manner. Now comparison to silicon is notoriously difficult, even for well-established and stable processes, so we’ll permit one level of abstraction and say it’s the smaller difference between the modeled current and SPICE configured in exactly the same manner. I can think of nothing better - it’s not a perfect situation, since SPICE objects to circuits with power nets (especially large MOS count circuits), see the limitations section in this article, and FastSPICE can be finicky for its own reasons. If you can recommend a better one, or come up with a closed-form model, I’d be one of many people who would love to hear about it.

Extraction writes its results, in the form of RC (L, K) values back to the binary database containing the physical data. From this database users set options and configuration flags to netlist the data to the required format, specifying which set of node names to use (schematic, layout, or arbitrary), and whether there should be any transformation or reduction of the data as the netlist is written.

I want to briefly mention reduction here, and raise a potential issue for you to consider.

Signal net reduction aims to take a complex interconnect graph (tree-like, but complicated by the distributed coupling capacitors) and create a simpler model that exhibits the same behavior at the source and sink nodes (as measured by arrival time and slew rate). Many of the techniques employ a multi-point moment-matching approach that can be made exact, given an upper frequency bound, merely by taking more moments into account. The Pade (and its descendents PVL, MPVL, SyPVL, etc), Arnoldi, and PRIMA methods are in contemporary use in many EDA reduction and timing analysis tools today. Other approaches are local node elimination, topology-based node reduction, and truncated balanced realization (TBR) methods. The one thing that all these approaches have in common is the objective - time of flight and arrival slew rate.

Power distribution networks are different beasts. Firstly, they’re several orders of magnitude more complex, as measured by element count. I’ve worked on ground nets containing almost 1 billion resistors - hundreds to thousands is more common for the vast majority of signal nets. In addition, applying a moment-based reduction to a power net can significantly alter the characteristic impedance, and this is the very thing you’d want to keep controlled.

Good power net reduction starts with the following:

• Series merging: resistor elements in series, with nothing attached to the intermediate node, can be merged into a single resistor without affecting the circuit behavior.
• Parallel elimination: resistors in parallel (for instance, via arrays) also can be merged into a single resistor.
• After maybe iteration around the series-merging and parallel-elimination loops a few times, R_MIN elimination can be applied (where resistors less than a user-defined minimum value can be eliminated from the circuit).

At this point, the number of resistors in the power networks has usually been reduced by one, maybe two, orders of magnitude (depending on how high the user set R_MIN.) What doesn’t change, or changes only in a minor way, is the topology or structure of the power net - a mesh-like structure before reduction, it remains a similarly structured mesh after reduction. The big difference is in the simpler connection between layers (due to via merging through parallel elimination), and simpler branches (due to elimination of resistors through series merging). Techniques for further reduction are currently being actively pursued; multigrid methods, standard and algebraic, appear promising.

Having compared transient simulation results between a) moment-matching reduction, and b) power net series-parallel-R_MIN reduction, using unreduced power networks as reference, I can report that the error injected using moment-based reduction was so significant as to be unreliable (impedance more than an order of magnitude off, circuit performance tens of percent off). And here’s my caveat - be very careful when you netlist and reduce your signal nets and power nets; apply reduction judiciously and appropriately.

In the first article in this series about voltage drop verification and analysis we discussed the components of the power distribution system, and briefly described the problem. The remaining articles in this series will describe solutions, targetted at each stage of the design process. We’ll start, in this article, with necessary physical data.

In working with power nets over the last decade or so, I’ve often been frustrated by the lack of any standard data format to enable power net parasitics data export from extraction tools to analysis tools. If you remain within the complete flow provided by a broadline supplier then you don’t need to worry about moving data , but if you want to introduce new, innovative analysis tools, you have to feed them the data they need. For this reason, many of the simpler power net analysis tools include their own power net extractors. These extractors are straightforward.

Power net extraction
Power net conductors are typically Manhattan shapes, except in analog/RF designs where non-orthogonal structures may be used. The metal shapes are fractured into ‘more manageable’ sizes, naming the intermediate sub-nodes.

Capacitance extraction precision depends to a large extent on determining the environment in which the metal element is placed. Only the simplest structures, like the parallel plate capacitor, have an analytical formula with good accuracy; for the vast majority of geometries, fringing and lateral capacitance dominate parallel or area capacitance. For power nets, though, the geometries are usually large in size and so the significance of fringing and lateral is reduced. Usually, then, a simple pattern matching algorithm gives acceptable accuracy for capacitance (to ground) of power net conductors.

Resistance extraction for simple geometries is simply the sheet resistivity multiplied by the geometry length and divided by the cross-sectional area. This is usually simplified to “square counting” - multiplying the resistance per square by the number of squares (geometry length / width). Some adjustment may be made at orthogonal abutments to account for current crowding. Vias are complex 3D geometries, but for power net extraction they can usually be merged into one ’super-via’ without too much degradation in accuracy. Those with a need for the utmost level of accuracy may employ 3D solvers on the via arrays, but this probably overkill for the majority of designs.

Finally, the RC data is written back to the physical database, from where it can be fed into the analysis tools, natively or though file I/O, when needed.

Parasitic data exchange formats
There are two commonly used file formats to exchange extracted parasitic data, the Standard Parasitic Exchange Format (SPEF) and the Detailed Standard Parasitic Format (DSPF). SPEF is the newer of the two, is an IEEE standard (part of IEEE 1481), and has explicitly-defined support for coupling capacitors. It’s also a much denser format than DSPF, thanks to its table-like indexing structure, but it suffers from having no standard method of describing resistor geometrical information.

DSPF, on the other hand, is verbose. DSPF files can easily be many times larger than SPEF files for the same design, and 5-10GB is not unusual. Coupling capacitors are not explicitly supported (since there’s no standard, each vendor extends DSPF in their own unique way, eliminating any chance of easy interoperability, and in one case actually double-counting coupling capacitors - so take care if you’re using this flow.) For our purpose here, though, DSPF has one advantage - with some setting of switches and controls in extraction and netlisting, a DSPF netlist can include resistor geometry and location information. While this isn’t absolutely vital for voltage drop analysis, it assists both visualization of results (maybe back-annotating to a GDS viewer or DRC analysis tool, e.g. Mentor’s Calibre RVE) and enables electromigration - more correctly current density - analysis (which tends to go hand-in-hand with voltage drop analysis).

Sadly, again, there’s no standard for annotating the DSPF file with resistor geometry information. Generally, though, there are two formats.

The first we shall call “element geometry format”, since it attaches relevant geometrical information to each resistor element contained in the DSPF. Each resistor declaration, without geometry, appears:

/* resistor declarations */
R<identifier> <node1> <node2> <Rvalue>

The geometry information is contained in a comment appended to the resistor declaration line, and typically includes the X, Y locations of node1 and node2, as well as the width, length and layer number of the resistor. If it’s a modeled resistor (to include temperature-dependent or voltage-dependent effects, for example, there may be a model identifier called out here too).

The second format we shall call “coordinate geometry format”, since it attaches less data to the resistor declaration line and relies upon additional content in the DSPF file.

/* sub-node declarations */
S<node1> <node1.x> <node1.y>
S<node2> <node2.x> <node2.y>
/* resistor declarations */
R<identifier> S<node1> S<node2> <Rvalue>

For the coordinate geometry format, width and layer are written into the comment field, while the length may or may not. If not, it can be calculated. Since these are Manhattan geometries, S<node1> and S<node2> will have identical X or Y coordinates. The absolute difference between the other, non-identical coordinates, gives the resistor length. Even if the length was given in the resistor declaration line, it’s a good idea to check the given and the calculated are the same. I’ve known them to be different.

Other physical data
Signal net parasitic data may needed, and back-annotated to the analysis netlist. If the currents are going to be computed, or stored during some transient simulation, signal net RC data is vital. After all, current comes from the switching MOS or logic gate charging a load capacitance. Also, this data is needed for ‘regular’ post-layout performance verification, even without voltage drop analysis, so it has to be available somewhere.

The VDD and GND voltage sources, their values and their locations must also be available.

The models for power and signal pad and pin electronics are, if present at all, usually contained in the analysis netlist.

So that’s it for the physical data requirements. We’re going to move on to modeling and deriving the current, starting in the next article with static or pseudo static approaches, and how these can be used for rudimentary voltage drop (and current density) analysis. Stay tuned.

Example extraction tools (not an exhaustive list)

• Star-RCXT (Synopsys)
• QRC (Cadence)
• Calibre xRC (Mentor)
• Columbus (Sequence)

The power distribution system delivers power and ground from outside the chip to each MOS device. Ideally, these voltages remain constant during the various modes of design operation, even as large switching currents are delivered. However, integrating a greater number of smaller, faster-switching and increasingly leaky devices on a single SoC work against this ideal situation. Power supply voltage variation reduces design performance, leading to - perhaps intermittent - functional failures. This makes a robust and reliable power distribution system critical to silicon success.

Many tools for performing voltage drop verification and analysis are available on the market, and this series of articles will describe many of the techniques that these tools employ, along with where their use is most appropriate, and their limitations.

For this introductory article we’ll describe the components of the power distribution system. From the power supply, down to the VDD-connected source or GND-connected drain terminals, these are in approximate order:

• The package interface to the external PCB, comprising a package pin, lead frame and bond wire, or for a C4¹ package, the solder bumps. While the resistance of these pin/package related components isn’t significant, the wire inductance can, when combined with the high dI/dt demanded by today’s high-speed interfaces, generate voltage variations at the pads that must be analysed.
• Many designs (flash memories, DC-DC convertors, image sensors and codecs, to mention just a few) contain on-chip voltage generators and regulators, and distribute this internally-derived voltage over the chip. In addition, power management components, such as footer or header cells, are increasingly present in SoC power distribution networks. These constructions can, however, defeat the implicit definition² of a power net used by many EDA tools, and so if your design will include these, be sure that your tool of choice can deal with this situation, perhaps by explicitly naming power nets for subsequent analysis.
• The power distribution interconnect itself comprises metal geometries on many metallization layers, connected by vias or via arrays. For the purpose of almost all analysis today this interconnect is considered to be purely resistive (with capacitance to ground). Two factors determine this: the first is that the extraction of inductance distributed throughout the power grid is not yet a solved problem for anything other than small contained regions (where return paths can be determined easily), and the second is that the resistive voltage drop swamps - for now - the inductive voltage drop (because the L and the dI/dt in this interconnect, even accumulated,
  remain small). One challenge, though, is that the number of resistors in the extracted power nets can be in the tens to few hundreds of millions. In a later article we’ll discuss power net reduction techniques and hierarchical analysis, along with other ways to enable efficient computation of these large networks.
• Adding decoupling on-chip is an effective way to control VDD voltage variation, since the decoupling circuitry can locally store charge to be made available at times when high current transients occur. Such decoupling has traditionally used MOS transistor gate capacitance (called decaps), but as VDD voltage scales down, sub-threshold and dielectric leakages within the decaps have come to limit their number, and their placement has to be carefully chosen to maximize their desired effect while minimizing high current draw. More recently, active decoupling circuitry has been included on high-speed designs, and this suffers from fewer undesirable characteristics.

Problem Formulation

where:

• VDD’ is the voltage monitored at the source terminal of each VDD-connected PMOS device.
• VDD is the (usually fixed) externally-provided power supply voltage connected to all VDD power pads.
• IR is the resistive voltage drop, accumulated for each path from the source terminal to the power pad
• L(dI/dt) is the inductive voltage drop, similarly accumulated for each inductive component from the source terminal to the power pad

Similarly, GND’ may be derived for all GND-connected NMOS drain terminals.

Note that VDD’, I and dI/dt may be fixed, static values or time-varying, depending on the kind of analysis that we wish to perform and the data available to us.

Further, note that determining the possibly time-varying value of VDD’, and attempting to keep its variation from VDD within, say, 10%, serves merely as a gating check and not as a detailed verification of design performance. For such verification the values of VDD’ would need to be somehow backannotated to the circuit and performance verified under voltage drop conditions. This will be discussed in later articles.

For now, let’s wrap up this introductory article. The second article will discuss what data is required in order to perform voltage drop verification and analysis.

Notes

1. C4: Controlled Collapse Chip Connect, an IBM innovation in the 1960s, is a packaging technology that flips over the chip, connecting it to the external system through an array of solder balls that are remelted during final assembly.
2. The implicit definition of a power net used by many EDA tools runs something like this: a net that resistively connects together a number (user-defined, default may be hundreds to thousands) of PMOS sources or NMOS drains, and passes to a fixed or time-varying voltage source (or other VDD/GND definition) through resistors or inductors only. Blocking capacitors are clearly illegal under this definition, as are the pass transistors that may be seen in power management or voltage regulation.

In the handful of articles published to date on this site on the subject of circuit simulation, we’ve visited - briefly, at least - the following:

• SPICE and derivatives
• Fast-SPICE
• Hierarchical circuit simulation
• State of the market

Recently, someone pointed out to me that this was all very interesting, and asked where would I predict the biggest advances will be in circuit simulation over the next few years. I’ve given this matter a lot of thought lately - I’ve had a lot of time on my hands - and while prediction is an incredibly risky business (and usually wrong the moment it is uttered; see DataQuest forecasts passim) this article draws some conclusions about what’s needed. I’ve also “shown my working” so you can see the thought process that arrived at these conclusions, and you can agree or disagree in the comments.

I’ve split my predictions into a couple of areas, identified by the vector forcing the change.

Process Technology

With process technology in the 10-50nm range, relying on current modeling and simulation technology will introduce increasing absolute and relative errors.. There are needs in a couple of areas:

• Precision beyond what the BSIM v4.5 model gives. The PSP model is still in an early stage of adoption, but this surface-potential-based model, the merger of the Philips MOS11 model and Penn State modeling efforts, offers sub-nV error with a 30-50% degradation of simulation runtimes. This degradation will, as it did for all model level changes in the past, be gradually reduced. Expect to see considerable work on improving the accuracy, usage modes and run-time efficiency of the PSP model.
• Corner analysis seldom gives worst-case performance for analog circuits, and often gives unnecessarily pessimistic results for digital circuits. Monte Carlo analysis needs hundreds of runs before any meaningful analysis can be performed. For this reason I expect to see a significant surge in the use of statistical circuit simulation in the next few years. This will require effort in characterizing not only the model parameters themselves (which we’ve been doing for years) but also the correlation between them (eg. for instance, between oxide thickness and VT0). Once the models are available, new statistical simulation techniques (response surface modeling or principal component analysis) reduce the number of discrete simulations that must be performed, while keeping the results within acceptable error limits.

Ever-Increasing Element Count

• Increasing analog (really, anything that’s no longer pure digital) content, and increasing use of asynchronous design styles (like GALS), place an increasing burden on the memory efficiency and run-time performance of circuit simulation. In addition, design performance characteristics are increasingly layout-dominated, requiring the simulation and analysis of parasitic dominated netlists containing maybe two orders of magnitude more elements than the original MOS count.
• Coupling, long the enemy of circuit simulation (both SPICE and Fast-SPICE) can no longer be ignored or approximated. Including the power and ground nets, finely-fractured signal nets that include coupling capacitors, and maybe distributed inductors or substrate resistors, cause the simulation effort to explode (as previously described in earlier articles). Yet some analysis can’t be performed without fully-extracted netlists.
• I forecast the coming together of circuit simulation and inexpensive distributed computing platforms. Xoomsys and Gemini DA are two commercial enterprises working in this area, though neither has released successful products at the time of writing. Magma’s FineSim SPICE claims to have parallel capability, but results are published only for a few CPUs, and no mention is made of incorporating power nets and other globally coupled nets. It’s definitely an interesting approach but one wonders just how scalable it is, beyond shared-memory and across a network. Other approaches to parallel or distributed SPICE involve preconditioning the circuit matrix in order to reduce the computation effort, perhaps to facilitate solution on distributed machines. So far the jury is out on these, as although the load time can be improved almost linearly with the number of machines, the solve time quickly bogs down. Innovation is required in this area for progress to be made.

Flow Integration

• Maintaining two separate flows - a digital, synthesis-driven flow, and an analog/mixed-signal schematic-driven flow - is becoming increasingly unsustainable as analog content and behavior increases. Co-simulation between Verilog or VHDL simulators and circuit simulators is now readily available, but too often requires much user effort to manipulate a netlist into shape. This has to be made much more seamless.
• Increasingly complex analog or mixed-signal designs are inefficiently described in schematic form, so expect to see more language-driven flows for A/M-S, in the same way that HDLs sprang up in the mid 1980s. Tools to successively refine designs will appear, filling the role that synthesis and optimization did for the digital flow. These won’t be universally applicable to all analog design, but small and medium sized blocks are already developed this way for applications which aren’t performance sensitive.

Recommended and reference reading

The SPICE Book, by Andrei Vladimirescu

Inside Spice: Overcoming the Obstacles of Circuit Simulation, by Ron Kielkowski

Electronic Circuit & System Simulation Methods, by Larry Pillagi

Circuit Simulation Methods and Algorithms, by Jan Ogrodzki

Computer Methods for Circuit Analysis and Design, by Jirí Vlach