All About EDA
All about EDA, VHDL/Verilog, Logic and Circuit Simulation, and more, from an Expert!
Archive for: March 2008March 10, 2008 Voltage drop analysis and verification - an introductionThe power distribution system delivers power and ground from outside the chip to each MOS device. Ideally, these voltages remain constant during the various modes of design operation, even as large switching currents are delivered. However, integrating a greater number … March 22, 2008 Voltage drop analysis and verification - physical data requirementsThe power distribution system delivers power and ground from outside the chip to each MOS device. This article describes the power and ground networks data that is required for voltage drop (and to some extent current density or electromigration) analysis, … March 24, 2008 Voltage drop analysis and verification - a brief aside on power net reductionApplying signal net (moment-matching) reduction to power distribution networks can significantly alter the characteristics of the post-reduction power network - enough to render the currents, the voltage drop, and the resulting performance analysis under the influence of (dynamic) voltage drop … March 28, 2008 Voltage drop analysis - a note on accuracy and quality of resultsTo ensure silicon success, voltage drop analysis tools - like all EDA tools - must at their most detailed give results that precisely predict final silicon behavior. Yet for much of the design process the chip is in an incomplete … Comments on multi-core HSPICE 2008.03 for post-layoutSynopsys recently announced a multi-core version of HSPICE (2008.03) that can handle, as well as pre-layout circuits, post-layout designs containing in excess of a million parasitic RCs. Prediction is a risky thing, but we called this a little while ago. … |
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