All About EDA
All about EDA, VHDL/Verilog, Logic and Circuit Simulation, and more, from an Expert!
Archive for: May 2008May 1, 2008 Simulation accuracy is not a function of RELTOL settingIn SPICE, RELTOL determines convergence across iterations. Why then is it being touted by Berkeley Design Automation as a means of controlling simulation accuracy? Experienced SPICE users know that RELTOL is to accuracy as grapefruit spoon is to eye surgery. … May 9, 2008 Voltage drop analysis and verification - piecewise-constant current sourcesIn this article we’re going to introduce the concept of time into voltage drop analysis, in the form of time-varying current sources attached to the extracted power grid. With this approach it is possible to perform a crude, abstracted voltage … |
||
|
