Category: Voltage Drop Analysis

Using simulation to derive peak currents has bee described elsewhere on this site. This article describes the various vectorless methods that are used for obtaining instantaneous currents, focussing on the techniques before briefly describing how static timing analysis and timed …

In this article we’re going to introduce the concept of time into voltage drop analysis, in the form of time-varying current sources attached to the extracted power grid. With this approach it is possible to perform a crude, abstracted voltage …

As an abstract description you can consider each power distribution network to be mesh-like, of varying sparsity, with voltage sources from external to the chip connecting at some (peripheral or distributed) locations on higher level metal layers, and with transistor …

To ensure silicon success, voltage drop analysis tools - like all EDA tools - must at their most detailed give results that precisely predict final silicon behavior. Yet for much of the design process the chip is in an incomplete …

Applying signal net (moment-matching) reduction to power distribution networks can significantly alter the characteristics of the post-reduction power network - enough to render the currents, the voltage drop, and the resulting performance analysis under the influence of (dynamic) voltage drop …

The power distribution system delivers power and ground from outside the chip to each MOS device. This article describes the power and ground networks data that is required for voltage drop (and to some extent current density or electromigration) analysis, …

The power distribution system delivers power and ground from outside the chip to each MOS device. Ideally, these voltages remain constant during the various modes of design operation, even as large switching currents are delivered. However, integrating a greater number …