All About EDA
All about EDA, VHDL/Verilog, Logic and Circuit Simulation, and more, from an Expert!
Category: Voltage Drop AnalysisOctober 14, 2008 Voltage drop analysis and verification - the two-step or decoupled approachThe vast majority of voltage drop analysis tools employ a two-step, or decoupled, method. in this, currents are acquired with the power net replaced by a constant voltage source. While this makes the problem much more tractable, it also serves … October 3, 2008 CTO Chat: Infinisim announce RASER. What’s the story?With the announcement of RASER, Infinisim targets large mixed-signal circuits that demand high-precision and rapid turnaround. Offering the first commercial realization of dynamic mixed-mode simulation, RASER pushes the state of circuit simulation art forward a step or two. Will it … June 30, 2008 Vectorless methods for deriving instantaneous currentUsing simulation to derive peak currents has bee described elsewhere on this site. This article describes the various vectorless methods that are used for obtaining instantaneous currents, focussing on the techniques before briefly describing how static timing analysis and timed … May 9, 2008 Voltage drop analysis and verification - piecewise-constant current sourcesIn this article we’re going to introduce the concept of time into voltage drop analysis, in the form of time-varying current sources attached to the extracted power grid. With this approach it is possible to perform a crude, abstracted voltage … April 2, 2008 Voltage drop analysis and verification - static (constant-current) sourcesAs an abstract description you can consider each power distribution network to be mesh-like, of varying sparsity, with voltage sources from external to the chip connecting at some (peripheral or distributed) locations on higher level metal layers, and with transistor … March 28, 2008 Voltage drop analysis - a note on accuracy and quality of resultsTo ensure silicon success, voltage drop analysis tools - like all EDA tools - must at their most detailed give results that precisely predict final silicon behavior. Yet for much of the design process the chip is in an incomplete … March 24, 2008 Voltage drop analysis and verification - a brief aside on power net reductionApplying signal net (moment-matching) reduction to power distribution networks can significantly alter the characteristics of the post-reduction power network - enough to render the currents, the voltage drop, and the resulting performance analysis under the influence of (dynamic) voltage drop … March 22, 2008 Voltage drop analysis and verification - physical data requirementsThe power distribution system delivers power and ground from outside the chip to each MOS device. This article describes the power and ground networks data that is required for voltage drop (and to some extent current density or electromigration) analysis, … March 10, 2008 Voltage drop analysis and verification - an introductionThe power distribution system delivers power and ground from outside the chip to each MOS device. Ideally, these voltages remain constant during the various modes of design operation, even as large switching currents are delivered. However, integrating a greater number … |
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