Circuit Simulation - the next generation?

Summary: Drawing this series of circuit simulation articles to an end, we take a look at some of the vectors that are forcing change in the circuit simulation arena. Although predictions are inevitably risky and rarely correct, some areas ripe for innovation - some of which are undergoing active research and development - are identifed. What will the circuit simulation environment look like in 2012? Read on...

In the handful of articles published to date on this site on the subject of circuit simulation, we’ve visited - briefly, at least - the following:

Recently, someone pointed out to me that this was all very interesting, and asked where would I predict the biggest advances will be in circuit simulation over the next few years. I’ve given this matter a lot of thought lately - I’ve had a lot of time on my hands - and while prediction is an incredibly risky business (and usually wrong the moment it is uttered; see DataQuest forecasts passim) this article draws some conclusions about what’s needed. I’ve also “shown my working” so you can see the thought process that arrived at these conclusions, and you can agree or disagree in the comments.

I’ve split my predictions into a couple of areas, identified by the vector forcing the change.

Process Technology

With process technology in the 10-50nm range, relying on current modeling and simulation technology will introduce increasing absolute and relative errors.. There are needs in a couple of areas:

Precision beyond what the BSIM v4.5 model gives. The PSP model is still in an early stage of adoption, but this surface-potential-based model, the merger of the Philips MOS11 model and Penn State modeling efforts, offers sub-nV error with a 30-50% degradation of simulation runtimes. This degradation will, as it did for all model level changes in the past, be gradually reduced. Expect to see considerable work on improving the accuracy, usage modes and run-time efficiency of the PSP model.
Corner analysis seldom gives worst-case performance for analog circuits, and often gives unnecessarily pessimistic results for digital circuits. Monte Carlo analysis needs hundreds of runs before any meaningful analysis can be performed. For this reason I expect to see a significant surge in the use of statistical circuit simulation in the next few years. This will require effort in characterizing not only the model parameters themselves (which we’ve been doing for years) but also the correlation between them (eg. for instance, between oxide thickness and VT0). Once the models are available, new statistical simulation techniques (response surface modeling or principal component analysis) reduce the number of discrete simulations that must be performed, while keeping the results within acceptable error limits.

Ever-Increasing Element Count

Increasing analog (really, anything that’s no longer pure digital) content, and increasing use of asynchronous design styles (like GALS), place an increasing burden on the memory efficiency and run-time performance of circuit simulation. In addition, design performance characteristics are increasingly layout-dominated, requiring the simulation and analysis of parasitic dominated netlists containing maybe two orders of magnitude more elements than the original MOS count.
Coupling, long the enemy of circuit simulation (both SPICE and Fast-SPICE) can no longer be ignored or approximated. Including the power and ground nets, finely-fractured signal nets that include coupling capacitors, and maybe distributed inductors or substrate resistors, cause the simulation effort to explode (as previously described in earlier articles). Yet some analysis can’t be performed without fully-extracted netlists.
I forecast the coming together of circuit simulation and inexpensive distributed computing platforms. Xoomsys and Gemini DA are two commercial enterprises working in this area, though neither has released successful products at the time of writing. Magma’s FineSim SPICE claims to have parallel capability, but results are published only for a few CPUs, and no mention is made of incorporating power nets and other globally coupled nets. It’s definitely an interesting approach but one wonders just how scalable it is, beyond shared-memory and across a network. Other approaches to parallel or distributed SPICE involve preconditioning the circuit matrix in order to reduce the computation effort, perhaps to facilitate solution on distributed machines. So far the jury is out on these, as although the load time can be improved almost linearly with the number of machines, the solve time quickly bogs down. Innovation is required in this area for progress to be made.

Flow Integration

Maintaining two separate flows - a digital, synthesis-driven flow, and an analog/mixed-signal schematic-driven flow - is becoming increasingly unsustainable as analog content and behavior increases. Co-simulation between Verilog or VHDL simulators and circuit simulators is now readily available, but too often requires much user effort to manipulate a netlist into shape. This has to be made much more seamless.
Increasingly complex analog or mixed-signal designs are inefficiently described in schematic form, so expect to see more language-driven flows for A/M-S, in the same way that HDLs sprang up in the mid 1980s. Tools to successively refine designs will appear, filling the role that synthesis and optimization did for the digital flow. These won’t be universally applicable to all analog design, but small and medium sized blocks are already developed this way for applications which aren’t performance sensitive.

Recommended and reference reading

The SPICE Book, by Andrei Vladimirescu

Inside Spice: Overcoming the Obstacles of Circuit Simulation, by Ron Kielkowski

Electronic Circuit & System Simulation Methods, by Larry Pillagi

Circuit Simulation Methods and Algorithms, by Jan Ogrodzki

Computer Methods for Circuit Analysis and Design, by Jirí Vlach