Comments on multi-core HSPICE 2008.03 for post-layout

Summary: Synopsys recently announced a multi-core version of HSPICE (2008.03) that can handle, as well as pre-layout circuits, post-layout designs containing in excess of a million parasitic RCs. Prediction is a risky thing, but we called this a little while ago.

In a recent (Mar 10, 2008) press release, Synopsys announced that the 2008.03 release of HSPICE offers significant performance enhancements. The first area of improvement is for single-processor machines, and while this in itself is useful for designers, with the processor clock speed stalled, or even reducing slightly in an attempt to manage power and thermal issues, these can at best be incremental improvements that users have come to expect over the lifetime of a successful software product such as HSPICE.

The second area is one we at AllAboutEDA find hugely exciting, and a great indicator of better things to come. It’s all part of the just-announced Synopsys plan for multi-core EDA world domination. HSPICE has offered a multi-threaded version for a little while, focussed on pre-layout designs (for a discussion of how SPICE scales with coupled structures, extracted data, etc, see this article.) In the 2008.03 HSPICE release, however, support is extended to fully-extracted post-layout netlists, containing in excess of a million parasitic RC components. Applying an approximate rule-of-thumb, and assuming that this million components includes power and ground nets (something Synopsys haven’t explicitly stated), we’re expecting designs of around the 50k to 100k MOS size to fall into this set.

For analog and mixed-signal (A/MS) components, or large AMS IP blocks verified externally before inclusion in a larger chip context, this is right in the sweet spot. Kudos to Synopsys. It’s going to be very interesting to see how the multi-core circuit simulation providers, such as Magma, Xoomsys and Gemini DA respond to this. We will, of course, keep you posted.

Notes
Improvements are in DC convergence, time-step control, netlist parsing and model performance.