CTO Chat: Infinisim announce RASER. What’s the story?

Infinisim this week came out of stealth mode to announce their introductory product, RASER, a transistor-level simulator aimed squarely at verification of large (>100k elements) mixed-signal circuits, and claiming SPICE accuracy as well as run-times around 50X faster. In order to get a better understanding of the technology behind the product I had a conversation with Infinisim’s CTO, Zakir Hussain Syed, resulting in this post. My hope and belief is that AllAboutEDA readers can gain more from this second-level of technology detail than a regurgitated reformatted press release.

Infinisim call the technology underpinning RASER “Real-Time Adaptive Simulation”, a realization of dynamic mixed-mode simulation (see [1], long the subject of research in academia. RASER builds on many known and well-characterized pieces of existing circuit simulation solutions: it uses re-implemented or optimized solvers, and well-established methods of solving the SPICE model’s underlying analytical equations - there’s no pre-characterization of tabular models. The main contribution made by RAS is in the analysis, at each time point, of every partitioned circuit element (aka channel-connected component) and by determining its state (as defined by V, I, dV/dt, among others) selecting from one of a number of available solvers to optimally solve the partition, maintaining boundary conditions within the user-determined SPICE accuracy (abstol, reltol, or similar.)

You can see how performance and capacity are obtained. Some examples:

• Areas of the circuit with low activity can have their results computed at longer intervals. A longer time-step means lower computation effort, which in turn means higher performance.
• In addition, areas of the circuit may be latent, or experiencing a low rate of change, and by limiting unnecessary computation additional gains can be obtained here.

Many of today’s high-performance mixed-signal designs have complex multi-rate behaviours, with PLL/clock-recovery or clock-generation circuits being the classic stiff system. RASER joins Fast-SPICE in attempting to minimize the amount of computation - calculating smaller matrices, or fewer active partitions, less frequently - while remaining within tight tolerances. Now, those of you who know me and my history, know that I am a huge fan of Fast-SPICE for memory, for digital, and for digitally-dominated mixed-signal circuits. I remain so. But where the demand for precision is in the microvolt and the picosecond, Fast-SPICE can descend into what I call “parameter-setting paralysis” where the user spends weeks - or longer - trying to identify the control and configuration parameters that afford the required level of precision. And sometimes the required level is unobtainable. So this is interesting stuff!

One of the questions I was eager to address is related to performance of the simulator when coupling is increased - that is, how does run-time degrade as designers increase the parasitic data content, going from pre-layout simulation to extracted post-layout with RCC signal nets, and then to extracted post-layout with RCC signal net and RC power nets. I wrote of how SPICE scales under these conditions in the “limitations” section of a previous AllAboutEDA article on SPICE. You may ask “why simulate with the power distribution network attached?”, and it all comes down to precision. If you’re trying to simulate a 10Gbps SerDes then your margin of error is pretty slight; the bit time is 100ps, but edge placement precision is desired in the single-digit picosecond. Both the absolute and relative error in your simulation tool must be less than the variations you’re trying to analyze, and the variation induced by dynamic voltage drop is more than the few picosecond precision the SerDes spec calls for.

RASER addresses this in several ways. Firstly, I’m thrilled to see that it simulates concurrently active devices and power nets - the distribution of currents is more correct, and the performance characteristics of the circuit under the influence of voltage drop can be more precisely obtained using this direct approach, rather than the decoupled methods that many solutions employ [2]. A linear network solver aims to solve efficiently the large RC power net. Consider the whole circuit being simulated in SPICE, where the entire matrix must be solved for each time-step, and the computation effort for the denser VDD/VSS-including matrix is significant. With RASER, partitions connected to the power net are evaluated only if necessary. Like ripples in a pond, the effect of a power net node changing diminishes with “electrical distance” - and cumulative capacitance of diffusion and decoupling is intended to keep this region of influence small. I am intrigued how this worked in practice - for example, consider what happens when several large stones are dropped in the pond close together in space and time. You’ve done this yourself, as a child, and seen the complex interference patterns spread and degrade. What does this mean to RASER when a large area of the circuit is subjected to significant activity induced by the power net, while the signal net side activity continues all the while. I would be only too happy to see some customer benchmarks that show a) pre-layout, b) post-layout with fully-extracted signal nets, and c) post-layout with fully-extracted signal and power nets.

So, to finish, if your complex mixed-signal circuits demand tight levels of time and voltage precision, yet exceed SPICE capacity, you’ve got few alternatives. One is to try Fast-SPICE, with the potential for “parameter-setting paralysis” and the possibility you’ll miss critically important transitions. Another alternative is to try co-simulation, and wrestle with the issues around interface elements - you may catch gross design problems, but subtle errors like noise are difficult to identify. Finally, you might try and shovel your whole circuit into SPICE, and wait the heat life of the universe before answers appear. And finally, you might, just might, find that RASER has something of value for you. I can’t say for sure, as I don’t know your exact requirements, but I encourage you to consider all alternatives, and Infinisim have picked a class of circuits poorly served elsewhere. I’d be interested to hear any direct user feedback, so feel free to add your comments to this post below.

Notes.

1.For a good introduction to dynamic mixed-mode simulation, you can do no worse than to check out either
Al Davis’s 1991 Ph.D. dissertation, or the 1995 ISCAS paper by Zakir Hussain Syed and David Overhauser, in their pre-Simplex days, Automatic Dynamic Mixed-Mode Simulation, through Network Reconfiguration [IEEE membership required].

2.Stand by for a forthcoming AllAboutEDA article on the differences between direct and decoupled methods for voltage drop analysis.