“I believe that within five years only two EDA companies will survive. We will therefore be one of these two big companies, or we will have been bought by one of them.”

Wow. That’s a staggering assertion, and enough to make this life-long EDA guy sit up and notice. It’s either incredibly bold and ballsy or a plea to be acquired, and you can read it how you wish.

I can’t believe it’s evidence for a plea to be acquired, given that Magma’s market cap is less than 40% what it was this time last year. Even worse, the 52 week forecast is for $10, still far beneath the high water mark of the last 12 months ($15.44). So if it’s not acquisition time, maybe it’s a bold statement of intent, laying down a challenge to the other three broadline EDA companies. Let’s consider the evidence; taking on perhaps the greatest EDA franchise of synthesis; kicking Synopsys (a company unafraid of using litigation to assert and protect their rights) in the behind, to start off an expensive and extremely hostile action; buying Mojave to attack the LVS market; entering analog & mixed-signal design and verification. The desire to become a broadline supplier is pulling them in many different directions, and while the field may be excited, the impact on AEs, financial resources, and management attention is significant, if difficult to quantify.

Of course, you have to buy into the statement that there’ll only be 2 EDA companies in 5 years time - down from over 250 at the time of writing. It’s no surprise that we’re coming in to a time of consolidation - growth in EDA has been sluggish at best. With the bigger fish looking at the smaller fish as ‘temporarily outsourced initial R&D’, that’s still a lot of chewing and swallowing for the bigger fish.

I don’t buy into the two company thesis. Maybe it’s just Rajeev being Rajeev. Or maybe, just maybe, he’s channeling Joe Costello - the spirit of EDA past.

Note that this analysis gives current draw only, from which voltage drop may be derived. To determine performance variation under the influence of this voltage drop requires additional work. You could go to the effort of annotating the worst voltage drop at every component and run performance verification, but as described in an earlier article, you’ll end up with an extraordinary conservative worst-case, unlikely ever to be seen in chip operation. In addition, this conservatism leads to over-design - too much metal, on too many layers, dedicated to power routing. And with each additional layer adding about 10% to the die cost, some high-volume consumer designs may become economically unfeasible.

Instantaneous analysis

Imagine yourself in the middle of a typical synthesized circuit. All around you is activity, both topologically and temporally diffuse - that is, distributed in both time and location. Somehow we have to make sense of this seemingly semi-random activity, and to determine how the current is accumulated and distributed around the circuit. The good news is that we can use characteristics of the circuit to our advantage in performing an analysis to estimate, without running dynamic simulation at any level of abstraction, the instantaneous peak current draw.

How so? Well, it’s long been known, and it’s easy enough to verify, that the peak current draw in a circuit is coincident with or immediately after the active edge of the clock signal source - as the clock buffers distributed though the clock net - both global and local - switch state, and the register elements themselves also flip state. Because our objective is peak current draw we can and should assume that a) all clock gating cells are in pass-through mode, and b) all registers will change state.

Note that no state information is required for this analysis. If we want to complicate the analysis, trading off some additional computation for the sake of increased precision, we can determine topology or state-transferrence that would prevent downstream registers from switching (for instance, in back-to-back registers, the second register will switch in the clock cycle after the first one has switched.) To further complicate the register clocking-focussed analysis, pseudo-states (defined here as levels of inversion) can be propagated along cells in the clock path, and used to further refine the population of register elements that change state.

Now consider the combinatorial elements in the signal paths. Circuit activity propagates from register to register, along logic cones, initiated by the active edge of the clock signal. Some gates will pass signals, others will block them. In general, those gates earlier in the timing path, nearer the register outputs, contribute a greater amount to the current draw than do those gates further away. In the same spirit as described above for combinatorial cells in the clock path, analysis of states or inversion levels can be used to refine the potential activity and current waveform at each of the gates or cells in the logic cone.

With these clock and cone analyses being performed after the circuit has been levelized, currents are then accumulated and the peak current draw for the entire circuit can be determined. If placement information is available to the tool, regional activity at a chosen level of granularity can be determined.

These time-based current waveforms can then be output from our newly-developed tool as piecewise linear or piecewise constant current sources, and attached to the extracted power grid model (described in a previous article) to that peak voltage drop can be determined. Post-processing in the form of filtering, sorting, and bucketing can give users a text-based report of worst voltage drop nodes. With additional work, data can be back-annotated to a schematic or layout view in order to provide the layout engineer with additional information so that layout can be improved, perhaps by widening or adding metal, or by adding or relocating decaps.

Methods based on static timing analysis

The arrival time, duration and edge sense of switching events as they impinge on all cells in the synthesized design can be obtained from any static timing analysis tool. Post-processing this output report for use as input to the computation flow described in the section above short-cuts a lot of the analysis steps described. The expense, of course, is the interruption of static-timing analysis, and post-processing a few gigabytes of report file. Building this analysis into STA, though, reduces much inefficiencies.

Methods based on timed ATPG

Timed ATPG is a generalization of the more usual ATPG problem. Where regular ATPG aims to distinguish between a fault and a fault-free circuit, and to provide a vector that demonstrates that difference, timed ATPG finds an input vector that satisfies both functional and timing behaviour. PODEM-based timed ATPG has been criticised for sluggish performance when analyzing large circuits, driving much work on pre-characterising intermediate analyses, resulting in superior run times. With timed ATPG, the maximum instantaneous current through supply lines can be calculated (see the Krstic and Cheng paper from DAC97.)

In this article we’re going to describe replacing the constant-current sources, annotating instead time-varying piecewise-constant current sources. The locations, or tap points, to which these sources are attached is as before, namely either at the lowest or intermediate nodes in the power net. The diagram below shows the approach this methodology takes.

Much of this article describes alternative methods of calculating the value of these piecewise-constant current sources, and the approaches used to determine the granularity in the time domain.

Calculating these abstracted time-varying currents can be done in several ways, generally falling into one of the following two most common methods:

• Vector-dependent, or simulation-driven, methods
• Vectorless methods, usually static-timing driven (the subject of tomorrow’s article)

Vector-dependent methods

Like all simulation-driven verification, whether RTL, gate or transistor-level, these methods are extraordinarily computationally intensive. There are methodologies that employ RTL simulation to discern discrete time periods of most significant circuit activity, and use these periods, cut out with appropriate initialization sequences, as stimulus to drive the voltage drop analysis, and these do help to reduce the burden somewhat.

Abstracting information from simulation, through SAIF or verbose VCD files, is possible, as is the option to vary the time-granularity of the current sources through averaging segments. In figure 2 above, 5 segments are shown. The compute effort could be reduced by averaging segments 1 and 2, and segments 3 and 4. The cost would be to precision. Averaging across the entire time interval would give good average currents for current-density analysis, or for static voltage drop analysis (as in figure 1 above.)

Given a switching interval (or its inverse, frequency), it is possible to calculate the current for each node, for each time interval, using the equation I = 0.5 * effective_load_capacitance * VDD^2 * effective_frequency. These are the values plugged into the index tables of the piecewise current model.

One of the most-repeated complaints about all vector-driven methods is that it is difficult to find the vector pairs or patterns that maximally draw current from the power grid, and that using user-defined patterns tends to underestimate the voltage drop and failing to identify all potential problem areas. There’s an element of truth in this argument, and I am in broad agreement with it. For gate-level circuits, a successful approach to identify such vector pairs has been developed using a multi-objective genetic algorithm (see Yi-Min Jiang’s paper in ISLPED99.) This approach, though, like all two-step approaches (which in step one compute currents and in an independent step two compute their accumulation and distribution within the power grid) abstract away some critical information. We’ll return to this in a later article, when we discuss in detail the two-step approaches and their limitations.

In the next article we’ll discuss the vectorless methods.

So it was with reddening cheeks and mounting blood pressure that I read on SCDsource (the redoubtable Richard Goering serving as editor-in-chief) an “In My Opinion” piece written by Paul Estrada of Berkeley Design Automation and entitled “Don’t compromise on true SPICE accuracy.” The thrust of this piece is that accuracy of simulation is critically important and the evidence given to support the main assertions is this:

…we ran a true Spice accurate simulator on a production analog-to-digital converter (ADC) with a relative tolerance (RelTol) of 1e-3 (Spice default), and then repeated the run with a RelTol of 1e-2 (a greatly relaxed tolerance) to approximate 0.1% inaccuracy and 1% inaccuracy respectively.

Pi, on this you’re wrong. Or you’re gargling bong water.

RELTOL is the ratio between the numerical answers computed for the current and previous iterations. We users usually increase it a little if we want to improve DC convergence, but there’s a balance - setting it too high gives us the SPICE equivalent of the blue screen, the “timestep too small” error. There’s an explanation of how RELTOL affects convergence in note 3 of an AllAboutEDA SPICE article. But that’s all RELTOL is, a method of controlling what delta voltage value across iterations causes “convergence”; it has nothing to do with simulation accuracy. It affects local truncation error, which in turn affects numerical noise, but using it as a method of controlling simulation accuracy is bad.

And here’s the thing. I’ve been saying my whole working life in semiconductor or EDA that EDA tools are just that: tools. We can use them crudely, like trying to craft a finely-fitted dovetail joint with an axe. Or we can become craftsmen, serving time as an apprentice and learning how to use the tools with power, refinement and elegance. Changing RELTOL and asserting it changes the simulation accuracy (or precision) is an elementary error, and one that jars particularly because one of the main selling points of Berkeley’s Analog FastSPICE is its elegant convergence.

This is an intriguing approach - using off-the-shelf acceleration hardware hasn’t been something the EDA industry has taken to, preferring instead to design and make their own (see hardware accelerators, emulators, and other attempts passim.) We’ve predicted here the move to distributed computing, multi-core and multi-threading, and OmegaSim GX is part of that move. Accelerating MOS evaluation is a great first step, and I’d be really interested to see some real, open and transparent benchmarking (something most EDA software licensing expressly prohibits, by the way.)

In addition, the number of MOS evaluations increase hugely in tightly-coupled circuits; fully-extracted post-layout netlists including a large number of fine-granularity coupling capacitors and a full power and ground distribution system create havoc in SPICE and Fast-SPICE alike. I’d be curious to see, as the solve-load ratio changes with increasing coupling, how GX performs.

The primary variation in the capability offered by voltage drop analysis tools is in what gets connected to this power distribution network. On the chip itself there will be a PMOS source at the VDD-connected contact, and an NMOS drain at the GND-connected contact, but in the voltage drop analysis tool, like all EDA tools, there’s going to be a ‘modeled equivalent’ of the transistor. In this article we’re going to introduce the simplest of all possible models, a constant-current source.

A stylized description is given in the following diagram:

The solder bumps at the top-most level connect to a coarse grid. Below this are metal layers that distribute power in various directions:

• x direction; for instance, the power route contained within each standard cell entity, connected by direct abutment to adjacent neighbors.
• y direction; for instance strapping and feed-throughs to connect power from one stick of gates to an adjacent one (perhaps interdigiated).
• both directions; for instance, power rings surrounding embedded cores and memories, with connections to the next higher and next lower levels.

Each intersection, in each layer, has a capacitor connected to ground.

In this stylized description, MOS or gate currents are modeled by a constant-current source. There are several questions designers need to consider when using this approach:

1. How many will there be?

   The number of current sources can be as many as the number of MOS elements attached to the power net. In the case where a large, pre-characterized IP block (core, or memory, for instance) is instantiated, it’s common to take the peak I(VDD) figure, and divide it by the number of expected taps at the power ring/core top-level to get an estimated peak current per tap. In the absence of detailed design information, user may define an expected number of taps, based on prior design experience.

2. What will their value be?

   There are many methods to determine the value of the constant-current source, including:

   • A user-defined estimate, perhaps specified by instance name, die x,y region; or by wildcarding the instance name.
   • Each MOS transistor can be analyzed, and given a user-supplied estimate of the switching frequency (again, possibly modified by die x,y region), the I(max) of the MOS can be calculated as 0.5*load_cap*frequency*VDD^2
   • The I(DSAT) of each MOS can be used, modified by x,y region again.
   • In the example given above, where a pre-characterized RAM or IP block is instantiated, distributing the known peak current, I(MAX) over N taps results in I(MAX)/N per tap.
   • With the clock network alone constituting anywhere from 30% to 70% of a high-performance digital design’s current draw, some detailed analysis of this network, suitably back-annotated with VDD and GND can give a good first-level estimate of expected peak current.
3. Where will they be located?

   The taps will be located at the interface between the power net and the switching entity, typically at the contact layer. For IP blocks and RAMS the interface is, for these static currents, at the power rign of the instantiated block.

4. What kind of analysis is supported?

   At the taps for which current sources have been applied, the voltage VDD’ (equal to VDD - IR) has beeb calculated. This gives us the DC drop for this set of estimated currents, without inductive drop, and without the current contribution made by decoupling caps - in short, this analysis assumes all current will be coming from off-chip, through the power or ground bond pads.

   This is a slightly unreal situation, and since decaps typically provide around one half of the peak current requirements, serving to increase the regulation, the computed VDD’ is not terribly precise.

   So this analysis is limited to roughly checking if the VDD’ varies from nominal VDD by more than the budgetted variance (as well as a quick check of the DC current density though the power net conductors - see a future article). Performance verification under this DC drop value can be undertaken — some attempts have been made, particularly with static timing tools, to take this set of VDD’ values, back-annotate them to the circuit, and recalculate the new critical path timing value — but it gives a result of poor precision that does not necessarily approach the upper bound of variance, because there are no dynamic voltage gradients that would exist on the real chip.

   Also, if all the current taps are peak values, or estimated conservatively, the VDD’ value is going to be extremely conservative.

At best this analysis, using constant-current values of varying degree of precision, can give a very rough idea of the robustness of the power net. Expected results from this analysis should be:

• Does the VDD variation meet budgetted value, within 50% or so?
• Is the DC, unidirectional current density within acceptable limits for the metallization and via designs?
• Are there any gross errors in the power net - things like disjoint net segments, where power has not been connected, or current starving to the MOS because of inordinately high power net resistance (too few vias, or conductors laid out too narrow.)
• Is there too little VDD variation? This could mean that too much metal, in tracks laid down too thick, and on too may metal layers, has been dedicated to the power net. This compromises routing resources for signal nets, and wastes metal layers. At around 5% to 10% of die cost per upper metal layer, it pays to be economical with power routing.