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	<title>Comments on: Gemini uncloaks, announcing threaded SPICE. We talk with them to find out more.</title>
	<link>http://www.allabouteda.com/gemini-uncloaks-announcing-threaded-spice-we-talk-with-them-to-find-out-more/</link>
	<description>All about EDA, VHDL/Verilog, Logic and Circuit Simulation, and more, from an Expert!</description>
	<pubDate>Tue, 07 Feb 2012 08:52:38 +0000</pubDate>
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		<title>By: Arvel Peterson</title>
		<link>http://www.allabouteda.com/gemini-uncloaks-announcing-threaded-spice-we-talk-with-them-to-find-out-more/#comment-14515</link>
		<dc:creator>Arvel Peterson</dc:creator>
		<pubDate>Wed, 02 Jun 2010 20:03:40 +0000</pubDate>
		<guid>http://www.allabouteda.com/gemini-uncloaks-announcing-threaded-spice-we-talk-with-them-to-find-out-more/#comment-14515</guid>
		<description>&lt;i&gt;There are a lot of big claims from Gemini. I know from my experience at Mentor Graphics with the FastSPICE tool Mach TA that it can take man-years of development effort just to get the parser working robustly for HSPICE, let alone adding Spectre and Verilog-A into the mix. That&#8217;s a lot of productivity out of a small group of developers in such a short period of time. I wish them all of the success in the SPICE world. The start-up companies are offering the most innovation in the SPICE space for now. I&#8217;d love to see a head-to-head live benchmark of: Gemini, Infinisim, HSPICE, Spectre, Berkeley DA Analog Fast SPICE. Maybe we could get Sun or Intel to provide the hardware, then allow the teams to tune their results for one week on the condition that they show the results publicly, let&#8217;s say at a design conference or trade show, along with a panel of judges to declare winners in several categories (ie. PLL, Converters, Extracted netlists, charge pumps, memories, etc.).&lt;/i&gt;
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		<content:encoded><![CDATA[<p><i>There are a lot of big claims from Gemini. I know from my experience at Mentor Graphics with the FastSPICE tool Mach TA that it can take man-years of development effort just to get the parser working robustly for HSPICE, let alone adding Spectre and Verilog-A into the mix. That&#8217;s a lot of productivity out of a small group of developers in such a short period of time. I wish them all of the success in the SPICE world. The start-up companies are offering the most innovation in the SPICE space for now. I&#8217;d love to see a head-to-head live benchmark of: Gemini, Infinisim, HSPICE, Spectre, Berkeley DA Analog Fast SPICE. Maybe we could get Sun or Intel to provide the hardware, then allow the teams to tune their results for one week on the condition that they show the results publicly, let&#8217;s say at a design conference or trade show, along with a panel of judges to declare winners in several categories (ie. PLL, Converters, Extracted netlists, charge pumps, memories, etc.).</i><br />
+1</p>
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		<title>By: Kevin Cameron</title>
		<link>http://www.allabouteda.com/gemini-uncloaks-announcing-threaded-spice-we-talk-with-them-to-find-out-more/#comment-661</link>
		<dc:creator>Kevin Cameron</dc:creator>
		<pubDate>Thu, 30 Oct 2008 08:02:14 +0000</pubDate>
		<guid>http://www.allabouteda.com/gemini-uncloaks-announcing-threaded-spice-we-talk-with-them-to-find-out-more/#comment-661</guid>
		<description>The problem here is that to verify an analog design you need to run a lot of corners. A parallel processing simulator by its nature has lower throughput than a single threaded simulator in CPU cycles, i.e. you're usually better off running 4 jobs on a 4cpu machine than 1 4-threaded job (4 times), so multithreading is not really a big plus.  Also, analog designers hate switching tools so the ramp up time to revenue is usually way too long for newcomers to survive. I expect one of Gemini, Xoomsys or Nascentric may survive, but I wouldn't like to have money riding on it.</description>
		<content:encoded><![CDATA[<p>The problem here is that to verify an analog design you need to run a lot of corners. A parallel processing simulator by its nature has lower throughput than a single threaded simulator in CPU cycles, i.e. you&#8217;re usually better off running 4 jobs on a 4cpu machine than 1 4-threaded job (4 times), so multithreading is not really a big plus.  Also, analog designers hate switching tools so the ramp up time to revenue is usually way too long for newcomers to survive. I expect one of Gemini, Xoomsys or Nascentric may survive, but I wouldn&#8217;t like to have money riding on it.</p>
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		<title>By: Simon</title>
		<link>http://www.allabouteda.com/gemini-uncloaks-announcing-threaded-spice-we-talk-with-them-to-find-out-more/#comment-659</link>
		<dc:creator>Simon</dc:creator>
		<pubDate>Thu, 30 Oct 2008 05:32:08 +0000</pubDate>
		<guid>http://www.allabouteda.com/gemini-uncloaks-announcing-threaded-spice-we-talk-with-them-to-find-out-more/#comment-659</guid>
		<description>I hear you on the productivity sink that full HSPICE netlist compliance can be - I've seen it take up to 10 man years to get it to the point where finding a defect became rare; where I define rare as "a less than monthly occurrence." But I've also seen 2 man years. 

As for the shoot-out, wouldn't that be nice? But I seem to recall at least one big EDA vendors End-User License Agreement expressly prohibiting publication of benchmark results, no matter if the benchmark ended in a win for them, a loss or a draw. Wonder if that's still the case.</description>
		<content:encoded><![CDATA[<p>I hear you on the productivity sink that full HSPICE netlist compliance can be - I&#8217;ve seen it take up to 10 man years to get it to the point where finding a defect became rare; where I define rare as &#8220;a less than monthly occurrence.&#8221; But I&#8217;ve also seen 2 man years. </p>
<p>As for the shoot-out, wouldn&#8217;t that be nice? But I seem to recall at least one big EDA vendors End-User License Agreement expressly prohibiting publication of benchmark results, no matter if the benchmark ended in a win for them, a loss or a draw. Wonder if that&#8217;s still the case.</p>
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		<title>By: Daniel Payne</title>
		<link>http://www.allabouteda.com/gemini-uncloaks-announcing-threaded-spice-we-talk-with-them-to-find-out-more/#comment-658</link>
		<dc:creator>Daniel Payne</dc:creator>
		<pubDate>Thu, 30 Oct 2008 05:09:12 +0000</pubDate>
		<guid>http://www.allabouteda.com/gemini-uncloaks-announcing-threaded-spice-we-talk-with-them-to-find-out-more/#comment-658</guid>
		<description>There are a lot of big claims from Gemini. I know from my experience at Mentor Graphics with the FastSPICE tool Mach TA that it can take man-years of development effort just to get the parser working robustly for HSPICE, let alone adding Spectre and Verilog-A into the mix. That's a lot of productivity out of a small group of developers in such a short period of time. I wish them all of the success in the SPICE world. The start-up companies are offering the most innovation in the SPICE space for now. I'd love to see a head-to-head live benchmark of: Gemini, Infinisim, HSPICE, Spectre, Berkeley DA Analog Fast SPICE. Maybe we could get Sun or Intel to provide the hardware, then allow the teams to tune their results for one week on the condition that they show the results publicly, let's say at a design conference or trade show, along with a panel of judges to declare winners in several categories (ie. PLL, Converters, Extracted netlists, charge pumps, memories, etc.).</description>
		<content:encoded><![CDATA[<p>There are a lot of big claims from Gemini. I know from my experience at Mentor Graphics with the FastSPICE tool Mach TA that it can take man-years of development effort just to get the parser working robustly for HSPICE, let alone adding Spectre and Verilog-A into the mix. That&#8217;s a lot of productivity out of a small group of developers in such a short period of time. I wish them all of the success in the SPICE world. The start-up companies are offering the most innovation in the SPICE space for now. I&#8217;d love to see a head-to-head live benchmark of: Gemini, Infinisim, HSPICE, Spectre, Berkeley DA Analog Fast SPICE. Maybe we could get Sun or Intel to provide the hardware, then allow the teams to tune their results for one week on the condition that they show the results publicly, let&#8217;s say at a design conference or trade show, along with a panel of judges to declare winners in several categories (ie. PLL, Converters, Extracted netlists, charge pumps, memories, etc.).</p>
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