The power distribution system delivers power and ground from outside the chip to each MOS device. Ideally, these voltages remain constant during the various modes of design operation, even as large switching currents are delivered. However, integrating a greater number of smaller, faster-switching and increasingly leaky devices on a single SoC work against this ideal situation. Power supply voltage variation reduces design performance, leading to - perhaps intermittent - functional failures. This makes a robust and reliable power distribution system critical to silicon success.

Many tools for performing voltage drop verification and analysis are available on the market, and this series of articles will describe many of the techniques that these tools employ, along with where their use is most appropriate, and their limitations.

For this introductory article we’ll describe the components of the power distribution system. From the power supply, down to the VDD-connected source or GND-connected drain terminals, these are in approximate order:

• The package interface to the external PCB, comprising a package pin, lead frame and bond wire, or for a C4¹ package, the solder bumps. While the resistance of these pin/package related components isn’t significant, the wire inductance can, when combined with the high dI/dt demanded by today’s high-speed interfaces, generate voltage variations at the pads that must be analysed.
• Many designs (flash memories, DC-DC convertors, image sensors and codecs, to mention just a few) contain on-chip voltage generators and regulators, and distribute this internally-derived voltage over the chip. In addition, power management components, such as footer or header cells, are increasingly present in SoC power distribution networks. These constructions can, however, defeat the implicit definition² of a power net used by many EDA tools, and so if your design will include these, be sure that your tool of choice can deal with this situation, perhaps by explicitly naming power nets for subsequent analysis.
• The power distribution interconnect itself comprises metal geometries on many metallization layers, connected by vias or via arrays. For the purpose of almost all analysis today this interconnect is considered to be purely resistive (with capacitance to ground). Two factors determine this: the first is that the extraction of inductance distributed throughout the power grid is not yet a solved problem for anything other than small contained regions (where return paths can be determined easily), and the second is that the resistive voltage drop swamps - for now - the inductive voltage drop (because the L and the dI/dt in this interconnect, even accumulated,
  remain small). One challenge, though, is that the number of resistors in the extracted power nets can be in the tens to few hundreds of millions. In a later article we’ll discuss power net reduction techniques and hierarchical analysis, along with other ways to enable efficient computation of these large networks.
• Adding decoupling on-chip is an effective way to control VDD voltage variation, since the decoupling circuitry can locally store charge to be made available at times when high current transients occur. Such decoupling has traditionally used MOS transistor gate capacitance (called decaps), but as VDD voltage scales down, sub-threshold and dielectric leakages within the decaps have come to limit their number, and their placement has to be carefully chosen to maximize their desired effect while minimizing high current draw. More recently, active decoupling circuitry has been included on high-speed designs, and this suffers from fewer undesirable characteristics.

Problem Formulation

where:

• VDD’ is the voltage monitored at the source terminal of each VDD-connected PMOS device.
• VDD is the (usually fixed) externally-provided power supply voltage connected to all VDD power pads.
• IR is the resistive voltage drop, accumulated for each path from the source terminal to the power pad
• L(dI/dt) is the inductive voltage drop, similarly accumulated for each inductive component from the source terminal to the power pad

Similarly, GND’ may be derived for all GND-connected NMOS drain terminals.

Note that VDD’, I and dI/dt may be fixed, static values or time-varying, depending on the kind of analysis that we wish to perform and the data available to us.

Further, note that determining the possibly time-varying value of VDD’, and attempting to keep its variation from VDD within, say, 10%, serves merely as a gating check and not as a detailed verification of design performance. For such verification the values of VDD’ would need to be somehow backannotated to the circuit and performance verified under voltage drop conditions. This will be discussed in later articles.

For now, let’s wrap up this introductory article. The second article will discuss what data is required in order to perform voltage drop verification and analysis.

Notes

1. C4: Controlled Collapse Chip Connect, an IBM innovation in the 1960s, is a packaging technology that flips over the chip, connecting it to the external system through an array of solder balls that are remelted during final assembly.
2. The implicit definition of a power net used by many EDA tools runs something like this: a net that resistively connects together a number (user-defined, default may be hundreds to thousands) of PMOS sources or NMOS drains, and passes to a fixed or time-varying voltage source (or other VDD/GND definition) through resistors or inductors only. Blocking capacitors are clearly illegal under this definition, as are the pass transistors that may be seen in power management or voltage regulation.

In the handful of articles published to date on this site on the subject of circuit simulation, we’ve visited - briefly, at least - the following:

• SPICE and derivatives
• Fast-SPICE
• Hierarchical circuit simulation
• State of the market

Recently, someone pointed out to me that this was all very interesting, and asked where would I predict the biggest advances will be in circuit simulation over the next few years. I’ve given this matter a lot of thought lately - I’ve had a lot of time on my hands - and while prediction is an incredibly risky business (and usually wrong the moment it is uttered; see DataQuest forecasts passim) this article draws some conclusions about what’s needed. I’ve also “shown my working” so you can see the thought process that arrived at these conclusions, and you can agree or disagree in the comments.

I’ve split my predictions into a couple of areas, identified by the vector forcing the change.

Process Technology

With process technology in the 10-50nm range, relying on current modeling and simulation technology will introduce increasing absolute and relative errors.. There are needs in a couple of areas:

• Precision beyond what the BSIM v4.5 model gives. The PSP model is still in an early stage of adoption, but this surface-potential-based model, the merger of the Philips MOS11 model and Penn State modeling efforts, offers sub-nV error with a 30-50% degradation of simulation runtimes. This degradation will, as it did for all model level changes in the past, be gradually reduced. Expect to see considerable work on improving the accuracy, usage modes and run-time efficiency of the PSP model.
• Corner analysis seldom gives worst-case performance for analog circuits, and often gives unnecessarily pessimistic results for digital circuits. Monte Carlo analysis needs hundreds of runs before any meaningful analysis can be performed. For this reason I expect to see a significant surge in the use of statistical circuit simulation in the next few years. This will require effort in characterizing not only the model parameters themselves (which we’ve been doing for years) but also the correlation between them (eg. for instance, between oxide thickness and VT0). Once the models are available, new statistical simulation techniques (response surface modeling or principal component analysis) reduce the number of discrete simulations that must be performed, while keeping the results within acceptable error limits.

Ever-Increasing Element Count

• Increasing analog (really, anything that’s no longer pure digital) content, and increasing use of asynchronous design styles (like GALS), place an increasing burden on the memory efficiency and run-time performance of circuit simulation. In addition, design performance characteristics are increasingly layout-dominated, requiring the simulation and analysis of parasitic dominated netlists containing maybe two orders of magnitude more elements than the original MOS count.
• Coupling, long the enemy of circuit simulation (both SPICE and Fast-SPICE) can no longer be ignored or approximated. Including the power and ground nets, finely-fractured signal nets that include coupling capacitors, and maybe distributed inductors or substrate resistors, cause the simulation effort to explode (as previously described in earlier articles). Yet some analysis can’t be performed without fully-extracted netlists.
• I forecast the coming together of circuit simulation and inexpensive distributed computing platforms. Xoomsys and Gemini DA are two commercial enterprises working in this area, though neither has released successful products at the time of writing. Magma’s FineSim SPICE claims to have parallel capability, but results are published only for a few CPUs, and no mention is made of incorporating power nets and other globally coupled nets. It’s definitely an interesting approach but one wonders just how scalable it is, beyond shared-memory and across a network. Other approaches to parallel or distributed SPICE involve preconditioning the circuit matrix in order to reduce the computation effort, perhaps to facilitate solution on distributed machines. So far the jury is out on these, as although the load time can be improved almost linearly with the number of machines, the solve time quickly bogs down. Innovation is required in this area for progress to be made.

Flow Integration

• Maintaining two separate flows - a digital, synthesis-driven flow, and an analog/mixed-signal schematic-driven flow - is becoming increasingly unsustainable as analog content and behavior increases. Co-simulation between Verilog or VHDL simulators and circuit simulators is now readily available, but too often requires much user effort to manipulate a netlist into shape. This has to be made much more seamless.
• Increasingly complex analog or mixed-signal designs are inefficiently described in schematic form, so expect to see more language-driven flows for A/M-S, in the same way that HDLs sprang up in the mid 1980s. Tools to successively refine designs will appear, filling the role that synthesis and optimization did for the digital flow. These won’t be universally applicable to all analog design, but small and medium sized blocks are already developed this way for applications which aren’t performance sensitive.

Recommended and reference reading

The SPICE Book, by Andrei Vladimirescu

Inside Spice: Overcoming the Obstacles of Circuit Simulation, by Ron Kielkowski

Electronic Circuit & System Simulation Methods, by Larry Pillagi

Circuit Simulation Methods and Algorithms, by Jan Ogrodzki

Computer Methods for Circuit Analysis and Design, by Jirí Vlach

In the handful of articles published to date on this site on the subject of circuit simulation, we’ve visited - briefly, at least - the following:

• SPICE and derivatives
• Fast-SPICE
• Hierarchical circuit simulation

Nassda bought HSIM to market in 2001, and while there’s been undoubted evolution in circuit simulation during the last few years, there’s still significant opportunity for innovation to advance the state of the art still further. Before we look at where these trail-blazing advances will come, let’s just take a moment to review the current state of play in the circuit simulation market.

“Regular” SPICE
We’ve already seen that a more modern implementation of the well-proven circuit simulation algorithms can result in a leaner and cleaner product. Cadence’s SPECTRE had for a while a significant performance and capacity advantage over HSPICE; however, these advantages are rarely sustainable in the long term, and HSPICE has already clawed back much, if not all, of the ground it had lost. Berkeley Design Automation (not to be confused with UC Berkeley) offers another implementation, adding some new algorithms that afford faster DC convergence and speed transient simulation.

You can change your “regular” SPICE simulator on a whim, of course, but that’s an incredibly risky proposition. Validation, characterization and qualification of a new SPICE simulator is a several person-year project; netlist syntax and semantics, configuration and control options, models and the interaction with simulator core, even output formats must be rigorously and exhaustively checked and compared. There are two other costs that are rarely considered beforehand, and which always bite hard.

• Maintaining two copies of models, libraries, etc, for the period of transition is a grotesquely under-estimated cost. For a fairly lengthy duration you’ll be developing and qualifying components for two simulators, striving for compatibility between the two.
• Your current simulator has bugs. Many bugs. Some of them you even know about and have long-established workarounds to deal with them. Your newer simulator also has bugs. Probably more of them, since it is less mature. Certainly different bugs. Identifying the common core capabilities that, bug free, work identically across the two simulators is hard, and may reduce the subset of capabilities to less than a designer needs. Incompatibilities result, and resolving these differences during design diverts scarce and precious resources from the critical job in hand.

For these reasons, SPICE is a very “sticky” tool. Once in broad use, replacing it - and all the infrastructure that’s been set up to feed the beast - is far from trivial. I’m not saying never change your simulator, or never give one of the newer simulators a chance. Just be careful in how you move from a successful evaluation to a broad deployment, and consider deeply all the implications and the ramifications before you negotiate that VPA.

Fast-SPICE
There’s plenty going on in the Fast-SPICE world as well. Synopsys may have the vast majority of this market sewn up, and be hoping that the XA option (an HSPICE solver engine bolted onto - or should that be into?) their Fast-SPICE offerings will defend against some of the more outlandish (and somewhat specious) claims from some competitors. There are - well, were - a few plucky little startups licking their lips at this opportunity, but Mentor has picked up ADiT and Magma has picked up ACAD, and to be frank their success as standalone enterprises hadn’t been stellar. Maybe with a bigger organization behind them things will be different. Infinisim remains in stealth mode at the time of writing, and it’s been a few years, so expect something from them soon.

Recommended and reference reading

The SPICE Book, by Andrei Vladimirescu

Inside Spice: Overcoming the Obstacles of Circuit Simulation, by Ron Kielkowski

Electronic Circuit & System Simulation Methods, by Larry Pillagi

Circuit Simulation Methods and Algorithms, by Jan Ogrodzki

Computer Methods for Circuit Analysis and Design, by Jirí Vlach

Introduction
In the second of these introductory computer simulation articles we covered Fast-SPICE, the second generation of circuit simulators. This article discusses the third generation of circuit simulation technology, the hierarchical tools.

Typical Applications
Initially aimed at the memory design and verification segment, HSIM rapidly took off in this area and expanded to analog/mixed-signal circuits (particularly stiff systems such as PLLs/DLLs) and large SOC designs containing tens of millions of transistors, many digital, and with the most critical to performance and challenging to verify being analog.

Later options provided for robust simulation of post-layout circuits, back-annotated with extracted data for signal and power nets, with unique algorithms to reduce parasitics without hugely impacting precision and performance. The application of these techniques to dynamic voltage drop and reliability analysis will be covered in a forthcoming series of tutorial articles here on AllAboutEDA.com.

Strengths
For large circuits where precision is key, and correlation to SPICE is paramount, HSIM offers capacity, performance and precision. It is easy to use, mirroring SPICE in many critical designer-relevant attributes (netlist, models, stimulus, configuration and control, etc), and robust in operation. It fits easily into existing design flows, supporting the latest needed capabilities (cosimulation, integration into analog design environments and back-annotation flows). Many parameters offer tuning for specfic needs, to give the designer freedom to trade-off precision and performance, but for many contemporary circuits, the default out-of-the-box behavior offers “enough” performance and “enough” precision to minimize the need for tinkering and tweaking.

Limitations
Like Fast-SPICE simulations, global coupling can challenge HSIM’s algorithms. While there are reduction and back-annotation capabilities available to minimize performance and precision loss due to modeling selectively-instantiated coupling, for larger circuits where the reduction is significant, these losses can accumulate and inject some error. Sadly, for circuits such as these, constructing a golden reference using SPICE is not possible.

Basic Operation
The initial attempt at hierarchical simulation was that offered in the Hierarchical Array Reduction (HAR) approach developed in Synopsys’ NanoSim. This approach works reasonably well for memory designs, and relies upon the stimulus remaining fixed during verification. First, the memory core cells are removed from the design, and user-supplied stimulus is applied to the circuit. This identifies the word and bit lines that will be activated by the stimulus, and hence the core bit cells on which this activity will impinge. During the second, simulation, phase, these necessary core cells are instantiated. Other cells in the core are either eliminated or merged together. In essence this is an automated static preconditioning of the circuit database under control of the user and the applied stimulus. Reduction in element count can be significant, with a commensurate increase in simulation performance and memory efficiency. Some degradation of accuracy in timing and current values results, so this approach has to be carefully characterized in order to ensure the loss in precision remains acceptable for your design.

A more successful and more generally applicable approach to hierarchical circuit simulation was pioneered by Nassda’s HSIM, which introduced two new innovations:

• Hierarchical storage, whereby repeated instantiations of the same fundamental element (of any kind, perhaps a bit cell, or a NAND gate, or a flip-flop), can be stored as a single template and instantiated on the fly during simulation without incurring any loss in precision of voltage, current, capacitance or their derivatives.

  

• Isomporphic matching, which eliminates unnecessary simulation cycles being spent on identical subcircuits at the same operating point or circuit condition. For example, adjacent memory bit cells experience coincident or near-coincident changes at many of their terminals. With isomorphic matching the need to repeat identical simulations is eliminated. A challenging aspect of this is matching the isomorphs dynamically - during pre-layout simulation the word-line (for instance) is a single node, and so all bit cells experience identical perturbation. Post-layout, however, the activity propagates along the word-line from the word-line drivers, and bit cells fall into and out of isomorph classes with this activity.

In addition, HSIM developed new algorithms to solve the hierarchical matrices orders of magnitude faster than SPICE, with only some small loss in SPICE precision. Further, adaptive time-step control techniques were developed that pushed forward the state of the art in this area, and the analog circuit detection was improved over all prior art. This latter was critical to gaining performance since HSIM could now recognize, without user intervention, which parts of the design could be simulated using precomputed lookup tables, and which would require full calculation of the analytical circuit equations.

Example Third Generation circuit simulators (not an exhaustive list)

• HSIM (Synopsys)
• UltraSim (Cadence)

Recommended and reference reading

The SPICE Book, by Andrei Vladimirescu

Inside Spice: Overcoming the Obstacles of Circuit Simulation, by Ron Kielkowski

Electronic Circuit & System Simulation Methods, by Larry Pillagi

Circuit Simulation Methods and Algorithms, by Jan Ogrodzki

Computer Methods for Circuit Analysis and Design, by Jirí Vlach

Introduction
In the first of these introductory articles on circuit simulation technology, we covered the initial generation of computer simulation software for transistor-level circuits, SPICE and its derivatives and descendents. This article focusses on the second generation of circuit simulators, examples of which became known as Fast-SPICE, that were born of necessity when custom, usually digitally-dominated, IC designs overtook the capacity and run-time capabilities of SPICE.

Several innovations in EDA enabled Fast-SPICE simulators, yet their application isn’t without some limitations and care has to be taken in modeling and simulation both to ensure the results obtained are valid. This article will describe their basic operation and where they may be most successfully employed.

Strengths
The main benefits offered by Fast-SPICE are performance and capacity when compared to SPICE - for the class of circuits for which it can be applied. Analog solvers have been integrated in Fast-SPICE to extend their utility to mixed-signal designs (see NanoSim’s XA for example, or PowerMill’s ACE option), and where the circuit size is too large for SPICE successfully to simulate, this was until the advent of the third generation of circuit simulators the only available option.

Limitations
The loss in precision compard to the gold standard of SPICE may be significant limitation for some circuits, but for many designs trading off a few percent in order to gain two orders of magnitude increase in simulation performance is too attractive to be ignored. There are, though, some things to be wary of with many Fast-SPICE tools:

1. Inductors can cause severe performance degradation, if they are instantiated in the circuit in such a way as to cause ringing (as in RLC circuits). The resulting explosion in number of events increases the computation effort, and kills performance.
2. For Fast-SPICE to retain performance coupling must be minimized - generally it is either ignored or approximated, under user control. Only the most critical coupling capacitors should be instantiated, with the others either split and grounded, or eliminated if very small. Additionally, coupling the MOS together through a power distribution network (PMOS through VDD, NMOS through GND) will, without significant reduction and an alternative solver, cause Fast-SPICE to grind to a halt.

Basic Operation
Fast-SPICE simulators were intially developed to offer high performance simulation of predominantly custom digital designs; analog and mixed-signal simulation capabilities were included several years after
initial release. At the time, circuits were becoming too big for SPICE to simulate efficiently within memory and performance limits, and though logic simulators such as Verilog-XL were already widely deployed, simulating dynamic logic or other custom styles wasn’t easily done.

Fast-SPICE starts with a realization that it is possible - desirable, even - to take advantage of certain circuit characteristics of custom digital designs. At the time, in the 1980s, the leadig edge process technology had a gate length of about 1um, and the propagation delay of a MOS device was faster, and therefore required more accuracy, than the wire delay between devices. Pre-layout functionality with some narrowly targetted RC backannotation on the signal nets for timing verification were the initial impetus for Fast-SPICE development. With short wide interconnect geometries and a power supply of 5V, interconnect coupling capacitors in the signal networks and voltage drop in the power network were at best second-order effects. The intended usage of Fast-SPICE, then, was MOS-dominated designs with low RC content, mostly or entirely digital, with loose coupling between the devices and nets.

The first innovation was to make the simulator event-driven, and by evaluating only those parts of the design on which the event impinged and caused a state or value change, to take advantage of the high degree of latency in these kind of designs. This requires the incoming netlist to be analysed, and channel-connected stages to be identified; each stage is then evaluated when an interface port voltage changes by more than a certain value (the greater the threshold, the faster the simulation performance, at the cost of precision). Though a single [G] matrix is created, computation is localized to one stage at a time - and since activity is fairly sparse in both time and location, the computation effort is far less than SPICE, which must compute the entire matrix.

The second innovation was to precompute for each size MOS model the relevant analytical equations and store the resulting charge, capacitance and current values in a lookup table. Then, during model evaluation, values are extracted or interpolated as required.

With these innovations implemented, Fast-SPICE became a reality, and for almost 15 years was the only alternative circuit simulation technology to SPICE. In the third article in this series, we’ll discuss the first hierarchical simulator.

Example Fast-SPICE simulators (not an exhaustive list)

• NanoSIM (Synopsys)
• UltraSim (Cadence)
• FineSim Pro (Magma)
• AuSim (Nascentric)

Recommended and reference reading

The SPICE Book, by Andrei Vladimirescu

Inside Spice: Overcoming the Obstacles of Circuit Simulation, by Ron Kielkowski

Electronic Circuit & System Simulation Methods, by Larry Pillagi

Circuit Simulation Methods and Algorithms, by Jan Ogrodzki

Computer Methods for Circuit Analysis and Design, by Jirí Vlach

Introduction
Accurate circuit simulation technology is the very foundation of EDA and IC design. The modeling and simulation of circuits enables function and other operational characteristics to be obtained before committing the part to manufacture, let along before providing the part to the end orinted circuit board manufacturer. Circuit simulation software such as SPICE and its derivatives, though one of the longest-serving technologies, is as essential today as it was 30 years ago at its introduction - the number of simulations required before sign-off, can be in the few thousands, especially if employing monte carlo simulation techniques.

Such computer simulation software isn’t without limitations, however, and knowing where and how best to apply it requires experience, thought, and some expectations of exactly what your simulations will reveal. This first circuit simulation article introduces the first generation of circuit simulators; later articles will describe the evolution of Fast-SPICE, hierarchical SPICE, and other approaches that aim to increase performance, precision and capacity, bringing the full benefits of computer simulation to the neophyte and experienced user alike.

Typical Applications
SPICE is used to determine the function and operating characteristics of ICs or components before committing to manufacture the part. Precision analog components, such as high-performance (high gain or wide bandwitch) op-amps or fast data converters, simply couldn’t be efficiently realized without using accurate circuit simulation and analysis. Though not large in transistor count their analog nature and need for precise simulation make SPICE necessary.

Larger in transistor count, mixed-signal ICs and components require SPICE - perhaps in a mixed-mode A/M-S simulator - in order to correctly analyze the behavior of the analog devices. During design, a Fast-SPICE simulator may be used to quickly determine approximate or relative characteristics, but for final verification and release to manufacturing there is no substitute for the absolute accuracy SPICE offers.

Many digital designs are based on components verified using SPICE. Cell libraries, I/O cells, embedded memories, and IP blocks are all characterized with SPICE. Finally, during the final verification of even large designs containing many millions of transistors and hundreds of millions of parasitic passive components, SPICE is used to determine performance of extracted sub-sections of the design, typically along critical paths or in interfaces between analog and digital sections.

Strengths
The main benefit SPICE simulators offer over other analog circuit simulators is precision. Like any software tool manipulating abstracted models, SPICE introduces numerical errors of its own (see below) in addition to the errors injected during the model characterization process. These errors, though, tend to be smaller than those found when using other approaches, and any stability problems tend to expose themselves as easily-discovered gross errors.

Limitations
While SPICE offers superior precision, it can only do so for circuits of limited size. Circuits greater than 100k MOS devices already experience some degradation in performance, though of course there’s no hard and fast rule since it depends on performance of the CPU, memory, I/O and disk sub-systems as well as circuit characteristics.

Simulation performance depends on many factors, and attempting to explain them all in detail is futile. We can, however, give some relative performance indicators.

1. The larger the circuit (measured in element count), the longer it will take to simulate. Run times for the same circuit pre-layout and post-layout (signal nets extracted only) can differ from 3X to 10X or more.
2. The more time-points to be calculated, the longer the circuit will take to simulate. Increasing the duration or complexity of applied stimulus increases the number of time-points. Changing the integration method will change the number of time-points. Reducing the tolerance (increasing the accuracy) will increase the number of time-points. High dV/dt or dI/dt will increase the number of time points.
3. Some circuit characteristics are naturally more computationally challenging to simulate. A tightly-coupled circuit (perhaps containing a clock or power grid) requires an enormous effort to compute every simulation time-point.

In general, at least to a first-level, circuit simulation performance is proportional to the number of circuit elements raised to the power of alpha, where:

• For loosely-coupled pre-layout circuits (no meshes or grids), alpha is approximately 1.4 to 1.5
• For loosely-coupled post-layout circuits (few coupling/floating capacitors only and no power grids), alpha is in the range of 1.5 to 1.7
• For tightly-coupled post-layout circuits (many coupling capacitors and power distribution grids), alpha is in the range of 2.0

Another drawback of SPICE is that the same time step must be applied to the entire circuit, even though some - or a great deal - of it may remain inactive during much of the simulation interval.

Finally, convergence can be an issue for some classes of circuits, particularly sensitive or high-gain ones. This is purely an issue with numerical integration, worse for some integration methods than others (notably, Newton-Raphson). As circuits get larger and include more non-linear behavior, convergence has become more difficult.

Basic operation
SPICE and its derivatives take as input an ASCII netlist containing a list of circuit elements and their interconnections, and construct from this a series of nonlinear differential algebraic equations (in matrix form, a variant of [G][v]=[i]). Solutions employ implicit integration methods, Newton’s method (Isaac, not Richard - a little SPICE humour there), and various manipulations of the sparse circuit matrix.

Before transient or other analysis is performed, a stable DC operating point must be set - this can either be calculated by SPICE or given by the user. For a circuit containing no non-linear or charge-storage devices, is simply a matter of inverting the [G] matrix and solving [v]=[G]^-1[i] in order to derive all circuit node voltages. Should the circuit contain non-linear devices, an initial estimate of the operating point is made and the node voltages computed with linear approximations for the non-linear models inserted. This technique is repeated until the solution converges - that is, node voltages and branch currents differ less than some defined (small) value on successive iterations.

Once a stable DC operating point has been found, SPICE can proceed to transient or other time-domain or frequency-domain analysis. We’ll consider only time-domain transient analysis here, since for most IC designers this is the most common usage mode. During transient analysis, SPICE attempts to compute an accurate approximation to the analytical solution for the given circuit at discrete time points using an implicit numerical integration method. Transient analysis pseudocode is given here, with additional information is contained in the notes below.

for each time-point between time=0 and time=TSTOP {
    using numerical integration, transform non-linear differential equations into algebraic equations
    guess initial node voltages
    converged = false
    while not converged {
        linearize non-linear diffeqs using Newton-Raphson
        solve equations
        if this solution differs from last solution by less than given tolerance {
            converged = true
        }
    }
}

Example SPICE and SPICE-like circuit simulators (not an exhaustive list)

• PSPICE (Cadence)
• SPECTRE (Cadence)
• HSPICE (Synopsys)
• ELDO (Mentor Graphics)
• SmartSPICE (Simucad)

In addition to other SPICE simulators available from academic and commercial sources, about a dozen semiconductor companies develop and maintain their own SPICE-derived or SPICE-like circuit simulators.

Notes
1. Circuit Elements include:

• Passive components, e.g. resistors, capacitors, inductors (of fixed or controlled values)
• Active components, e.g. MOS or bipolar transistors
• Fixed or controlled voltage or current sources
• Time-varying sources for circuit stimulus, e.g. sinusoids, or piecewise linear, generators

2. Matrix solution methods include:

• Cramer’s rule - rarely used as it is terribly inefficient for matrices of even small to moderate size
• Gaussian elimination or LU decomposition, with pivoting (to reduce instability)
• Cholesky decomposition, for symmetric positive definite matrices
• Stationary iterative methods, such as Jacobi and Gauss-Seidel
• Other iterative methods - for example Krylov subspace methods, such as the conjugate gradient method

3. DC operating point convergence is determined when both of the following occur:

1. Successive node voltage values differ by less than
• The expected node voltage * RELTOL (default: 0.1%), plus
• VNTOL (default: 1uV)
2. Successive branch current values differ by less than
• The expected branch current * RELTOL, plus
• ABSTOL (default: 1pA)

The number of iterations can be modified by the user, and once exceeded the simulator can apply Gmin or source stepping techniques to attempt to converge on a solution.

4. Integration methods used by circuit simulations can be chosen by the user to obtain the “best” results, as measured by the smallest error introduced (local truncation error or numerical noise), and the greatest stability (cancellation or reduction of error over time). Implicit integration methods are used because many circuit simulation problems are stiff in nature - the circuit contains vastly different time constants, and the time-step required to give accurate results under explicit integration methods would be impractical, resulting in very long run times. Possible implicit integration methods include:

• Backward Euler - offers a good compromise of accuracy and stability
• Trapezoidal - offers superior accuracy but can be too sensitive for some circuits and may induce oscillations in the solution
• Gear (Gear-2 or Gear-3) - offers superior stability while trading off some accuracy (in Gear-2) or performance (in Gear-3)

Recommended and reference reading

The SPICE Book, by Andrei Vladimirescu

Inside Spice: Overcoming the Obstacles of Circuit Simulation, by Ron Kielkowski

Electronic Circuit & System Simulation Methods, by Larry Pillagi

Circuit Simulation Methods and Algorithms, by Jan Ogrodzki

Computer Methods for Circuit Analysis and Design, by Jirí Vlach

Welcome to All About EDA, the site that is, well, all about EDA!

All About EDA is maintained by Simon Young, but contributions come from the EDA industry as well as practising IC designers in semiconductor companies. Simon has more than twenty five years in both IC design and EDA, and in addition to starting two companies has worked for, among others, TI, Intel, Synopsys, Nassda, Mentor Graphics, and GenRad.

You can reach Simon at info@AllAboutEDA.com