Second generation circuit simulation - Fast-SPICE

Summary: In the first of these introductory articles on circuit simulation technology, we covered the initial generation of computer simulation software for transistor-level circuits, SPICE and its derivatives and descendents. This article focusses on the second generation of circuit simulators, examples of which became known as Fast-SPICE, that were born of necessity when custom, usually digitally-dominated, IC designs overtook the capacity and run-time capabilities of SPICE. Several innovations in EDA enabled Fast-SPICE simulators, yet their application isn't without some limitations and care has to be taken in modeling and simulation both to ensure the results obtained are valid. This article will describe their basic operation and where they may be most successfully employed.

Introduction
In the first of these introductory articles on circuit simulation technology, we covered the initial generation of computer simulation software for transistor-level circuits, SPICE and its derivatives and descendents. This article focusses on the second generation of circuit simulators, examples of which became known as Fast-SPICE, that were born of necessity when custom, usually digitally-dominated, IC designs overtook the capacity and run-time capabilities of SPICE.

Several innovations in EDA enabled Fast-SPICE simulators, yet their application isn’t without some limitations and care has to be taken in modeling and simulation both to ensure the results obtained are valid. This article will describe their basic operation and where they may be most successfully employed.

Strengths
The main benefits offered by Fast-SPICE are performance and capacity when compared to SPICE - for the class of circuits for which it can be applied. Analog solvers have been integrated in Fast-SPICE to extend their utility to mixed-signal designs (see NanoSim’s XA for example, or PowerMill’s ACE option), and where the circuit size is too large for SPICE successfully to simulate, this was until the advent of the third generation of circuit simulators the only available option.

Limitations
The loss in precision compard to the gold standard of SPICE may be significant limitation for some circuits, but for many designs trading off a few percent in order to gain two orders of magnitude increase in simulation performance is too attractive to be ignored. There are, though, some things to be wary of with many Fast-SPICE tools:

Inductors can cause severe performance degradation, if they are instantiated in the circuit in such a way as to cause ringing (as in RLC circuits). The resulting explosion in number of events increases the computation effort, and kills performance.
For Fast-SPICE to retain performance coupling must be minimized - generally it is either ignored or approximated, under user control. Only the most critical coupling capacitors should be instantiated, with the others either split and grounded, or eliminated if very small. Additionally, coupling the MOS together through a power distribution network (PMOS through VDD, NMOS through GND) will, without significant reduction and an alternative solver, cause Fast-SPICE to grind to a halt.

Basic Operation
Fast-SPICE simulators were intially developed to offer high performance simulation of predominantly custom digital designs; analog and mixed-signal simulation capabilities were included several years after
initial release. At the time, circuits were becoming too big for SPICE to simulate efficiently within memory and performance limits, and though logic simulators such as Verilog-XL were already widely deployed, simulating dynamic logic or other custom styles wasn’t easily done.

Fast-SPICE starts with a realization that it is possible - desirable, even - to take advantage of certain circuit characteristics of custom digital designs. At the time, in the 1980s, the leadig edge process technology had a gate length of about 1um, and the propagation delay of a MOS device was faster, and therefore required more accuracy, than the wire delay between devices. Pre-layout functionality with some narrowly targetted RC backannotation on the signal nets for timing verification were the initial impetus for Fast-SPICE development. With short wide interconnect geometries and a power supply of 5V, interconnect coupling capacitors in the signal networks and voltage drop in the power network were at best second-order effects. The intended usage of Fast-SPICE, then, was MOS-dominated designs with low RC content, mostly or entirely digital, with loose coupling between the devices and nets.

The first innovation was to make the simulator event-driven, and by evaluating only those parts of the design on which the event impinged and caused a state or value change, to take advantage of the high degree of latency in these kind of designs. This requires the incoming netlist to be analysed, and channel-connected stages to be identified; each stage is then evaluated when an interface port voltage changes by more than a certain value (the greater the threshold, the faster the simulation performance, at the cost of precision). Though a single [G] matrix is created, computation is localized to one stage at a time - and since activity is fairly sparse in both time and location, the computation effort is far less than SPICE, which must compute the entire matrix.

The second innovation was to precompute for each size MOS model the relevant analytical equations and store the resulting charge, capacitance and current values in a lookup table. Then, during model evaluation, values are extracted or interpolated as required.

With these innovations implemented, Fast-SPICE became a reality, and for almost 15 years was the only alternative circuit simulation technology to SPICE. In the third article in this series, we’ll discuss the first hierarchical simulator.

Example Fast-SPICE simulators (not an exhaustive list)