|Summary: In SPICE, RELTOL determines convergence across iterations. Why then is it being touted by Berkeley Design Automation as a means of controlling simulation accuracy? Experienced SPICE users know that RELTOL is to accuracy as grapefruit spoon is to eye surgery. Read on...|
Those of you who know me well also know that I am liable to get a little bit cranky from time to time (I used to think it was my age, but it’s not getting any better as I wait for the AARP cards to come through the mail.) One of the things that most wraps me around the axle is EDA marketeers being economical with the truth, and misleading designers either by omission or by a lack of real, hard-won experience.
So it was with reddening cheeks and mounting blood pressure that I read on SCDsource (the redoubtable Richard Goering serving as editor-in-chief) an “In My Opinion” piece written by Paul Estrada of Berkeley Design Automation and entitled “Don’t compromise on true SPICE accuracy.” The thrust of this piece is that accuracy of simulation is critically important and the evidence given to support the main assertions is this:
…we ran a true Spice accurate simulator on a production analog-to-digital converter (ADC) with a relative tolerance (RelTol) of 1e-3 (Spice default), and then repeated the run with a RelTol of 1e-2 (a greatly relaxed tolerance) to approximate 0.1% inaccuracy and 1% inaccuracy respectively.
Pi, on this you’re wrong. Or you’re gargling bong water.
RELTOL is the ratio between the numerical answers computed for the current and previous iterations. We users usually increase it a little if we want to improve DC convergence, but there’s a balance - setting it too high gives us the SPICE equivalent of the blue screen, the “timestep too small” error. There’s an explanation of how RELTOL affects convergence in note 3 of an AllAboutEDA SPICE article. But that’s all RELTOL is, a method of controlling what delta voltage value across iterations causes “convergence”; it has nothing to do with simulation accuracy. It affects local truncation error, which in turn affects numerical noise, but using it as a method of controlling simulation accuracy is bad.
And here’s the thing. I’ve been saying my whole working life in semiconductor or EDA that EDA tools are just that: tools. We can use them crudely, like trying to craft a finely-fitted dovetail joint with an axe. Or we can become craftsmen, serving time as an apprentice and learning how to use the tools with power, refinement and elegance. Changing RELTOL and asserting it changes the simulation accuracy (or precision) is an elementary error, and one that jars particularly because one of the main selling points of Berkeley’s Analog FastSPICE is its elegant convergence.