Third generation circuit simulation - hierarchical simulation

Introduction
In the second of these introductory computer simulation articles we covered Fast-SPICE, the second generation of circuit simulators. This article discusses the third generation of circuit simulation technology, the hierarchical tools.

Typical Applications
Initially aimed at the memory design and verification segment, HSIM rapidly took off in this area and expanded to analog/mixed-signal circuits (particularly stiff systems such as PLLs/DLLs) and large SOC designs containing tens of millions of transistors, many digital, and with the most critical to performance and challenging to verify being analog.

Later options provided for robust simulation of post-layout circuits, back-annotated with extracted data for signal and power nets, with unique algorithms to reduce parasitics without hugely impacting precision and performance. The application of these techniques to dynamic voltage drop and reliability analysis will be covered in a forthcoming series of tutorial articles here on AllAboutEDA.com.

Strengths
For large circuits where precision is key, and correlation to SPICE is paramount, HSIM offers capacity, performance and precision. It is easy to use, mirroring SPICE in many critical designer-relevant attributes (netlist, models, stimulus, configuration and control, etc), and robust in operation. It fits easily into existing design flows, supporting the latest needed capabilities (cosimulation, integration into analog design environments and back-annotation flows). Many parameters offer tuning for specfic needs, to give the designer freedom to trade-off precision and performance, but for many contemporary circuits, the default out-of-the-box behavior offers “enough” performance and “enough” precision to minimize the need for tinkering and tweaking.

Limitations
Like Fast-SPICE simulations, global coupling can challenge HSIM’s algorithms. While there are reduction and back-annotation capabilities available to minimize performance and precision loss due to modeling selectively-instantiated coupling, for larger circuits where the reduction is significant, these losses can accumulate and inject some error. Sadly, for circuits such as these, constructing a golden reference using SPICE is not possible.

Basic Operation
The initial attempt at hierarchical simulation was that offered in the Hierarchical Array Reduction (HAR) approach developed in Synopsys’ NanoSim. This approach works reasonably well for memory designs, and relies upon the stimulus remaining fixed during verification. First, the memory core cells are removed from the design, and user-supplied stimulus is applied to the circuit. This identifies the word and bit lines that will be activated by the stimulus, and hence the core bit cells on which this activity will impinge. During the second, simulation, phase, these necessary core cells are instantiated. Other cells in the core are either eliminated or merged together. In essence this is an automated static preconditioning of the circuit database under control of the user and the applied stimulus. Reduction in element count can be significant, with a commensurate increase in simulation performance and memory efficiency. Some degradation of accuracy in timing and current values results, so this approach has to be carefully characterized in order to ensure the loss in precision remains acceptable for your design.

A more successful and more generally applicable approach to hierarchical circuit simulation was pioneered by Nassda’s HSIM, which introduced two new innovations:

• Hierarchical storage, whereby repeated instantiations of the same fundamental element (of any kind, perhaps a bit cell, or a NAND gate, or a flip-flop), can be stored as a single template and instantiated on the fly during simulation without incurring any loss in precision of voltage, current, capacitance or their derivatives.

  

• Isomporphic matching, which eliminates unnecessary simulation cycles being spent on identical subcircuits at the same operating point or circuit condition. For example, adjacent memory bit cells experience coincident or near-coincident changes at many of their terminals. With isomorphic matching the need to repeat identical simulations is eliminated. A challenging aspect of this is matching the isomorphs dynamically - during pre-layout simulation the word-line (for instance) is a single node, and so all bit cells experience identical perturbation. Post-layout, however, the activity propagates along the word-line from the word-line drivers, and bit cells fall into and out of isomorph classes with this activity.

In addition, HSIM developed new algorithms to solve the hierarchical matrices orders of magnitude faster than SPICE, with only some small loss in SPICE precision. Further, adaptive time-step control techniques were developed that pushed forward the state of the art in this area, and the analog circuit detection was improved over all prior art. This latter was critical to gaining performance since HSIM could now recognize, without user intervention, which parts of the design could be simulated using precomputed lookup tables, and which would require full calculation of the analytical circuit equations.

Example Third Generation circuit simulators (not an exhaustive list)

• HSIM (Synopsys)
• UltraSim (Cadence)

Recommended and reference reading

The SPICE Book, by Andrei Vladimirescu

Inside Spice: Overcoming the Obstacles of Circuit Simulation, by Ron Kielkowski

Electronic Circuit & System Simulation Methods, by Larry Pillagi

Circuit Simulation Methods and Algorithms, by Jan Ogrodzki

Computer Methods for Circuit Analysis and Design, by Jirí Vlach