Voltage drop analysis and verification - a brief aside on power net reduction

Extraction writes its results, in the form of RC (L, K) values back to the binary database containing the physical data. From this database users set options and configuration flags to netlist the data to the required format, specifying which set of node names to use (schematic, layout, or arbitrary), and whether there should be any transformation or reduction of the data as the netlist is written.

I want to briefly mention reduction here, and raise a potential issue for you to consider.

Signal net reduction aims to take a complex interconnect graph (tree-like, but complicated by the distributed coupling capacitors) and create a simpler model that exhibits the same behavior at the source and sink nodes (as measured by arrival time and slew rate). Many of the techniques employ a multi-point moment-matching approach that can be made exact, given an upper frequency bound, merely by taking more moments into account. The Pade (and its descendents PVL, MPVL, SyPVL, etc), Arnoldi, and PRIMA methods are in contemporary use in many EDA reduction and timing analysis tools today. Other approaches are local node elimination, topology-based node reduction, and truncated balanced realization (TBR) methods. The one thing that all these approaches have in common is the objective - time of flight and arrival slew rate.

Power distribution networks are different beasts. Firstly, they’re several orders of magnitude more complex, as measured by element count. I’ve worked on ground nets containing almost 1 billion resistors - hundreds to thousands is more common for the vast majority of signal nets. In addition, applying a moment-based reduction to a power net can significantly alter the characteristic impedance, and this is the very thing you’d want to keep controlled.

Good power net reduction starts with the following:

• Series merging: resistor elements in series, with nothing attached to the intermediate node, can be merged into a single resistor without affecting the circuit behavior.
• Parallel elimination: resistors in parallel (for instance, via arrays) also can be merged into a single resistor.
• After maybe iteration around the series-merging and parallel-elimination loops a few times, R_MIN elimination can be applied (where resistors less than a user-defined minimum value can be eliminated from the circuit).

At this point, the number of resistors in the power networks has usually been reduced by one, maybe two, orders of magnitude (depending on how high the user set R_MIN.) What doesn’t change, or changes only in a minor way, is the topology or structure of the power net - a mesh-like structure before reduction, it remains a similarly structured mesh after reduction. The big difference is in the simpler connection between layers (due to via merging through parallel elimination), and simpler branches (due to elimination of resistors through series merging). Techniques for further reduction are currently being actively pursued; multigrid methods, standard and algebraic, appear promising.

Having compared transient simulation results between a) moment-matching reduction, and b) power net series-parallel-R_MIN reduction, using unreduced power networks as reference, I can report that the error injected using moment-based reduction was so significant as to be unreliable (impedance more than an order of magnitude off, circuit performance tens of percent off). And here’s my caveat - be very careful when you netlist and reduce your signal nets and power nets; apply reduction judiciously and appropriately.