http://www.allabouteda.com/voltage-drop-analysis-and-verification-a-brief-aside-on-power-net-reduction/ All about EDA, VHDL/Verilog, Logic and Circuit Simulation, and more, from an Expert! Thu, 21 Aug 2008 02:30:14 +0000 http://wordpress.org/?v=2.3.1 http://www.allabouteda.com/voltage-drop-analysis-and-verification-a-brief-aside-on-power-net-reduction/#comment-16 nick Sat, 19 Apr 2008 18:32:14 +0000 http://www.allabouteda.com/voltage-drop-analysis-and-verification-a-brief-aside-on-power-net-reduction/#comment-16 very nice post very nice post

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