Voltage drop analysis and verification - an introduction

The power distribution system delivers power and ground from outside the chip to each MOS device. Ideally, these voltages remain constant during the various modes of design operation, even as large switching currents are delivered. However, integrating a greater number of smaller, faster-switching and increasingly leaky devices on a single SoC work against this ideal situation. Power supply voltage variation reduces design performance, leading to - perhaps intermittent - functional failures. This makes a robust and reliable power distribution system critical to silicon success.

Many tools for performing voltage drop verification and analysis are available on the market, and this series of articles will describe many of the techniques that these tools employ, along with where their use is most appropriate, and their limitations.

For this introductory article we’ll describe the components of the power distribution system. From the power supply, down to the VDD-connected source or GND-connected drain terminals, these are in approximate order:

• The package interface to the external PCB, comprising a package pin, lead frame and bond wire, or for a C4¹ package, the solder bumps. While the resistance of these pin/package related components isn’t significant, the wire inductance can, when combined with the high dI/dt demanded by today’s high-speed interfaces, generate voltage variations at the pads that must be analysed.
• Many designs (flash memories, DC-DC convertors, image sensors and codecs, to mention just a few) contain on-chip voltage generators and regulators, and distribute this internally-derived voltage over the chip. In addition, power management components, such as footer or header cells, are increasingly present in SoC power distribution networks. These constructions can, however, defeat the implicit definition² of a power net used by many EDA tools, and so if your design will include these, be sure that your tool of choice can deal with this situation, perhaps by explicitly naming power nets for subsequent analysis.
• The power distribution interconnect itself comprises metal geometries on many metallization layers, connected by vias or via arrays. For the purpose of almost all analysis today this interconnect is considered to be purely resistive (with capacitance to ground). Two factors determine this: the first is that the extraction of inductance distributed throughout the power grid is not yet a solved problem for anything other than small contained regions (where return paths can be determined easily), and the second is that the resistive voltage drop swamps - for now - the inductive voltage drop (because the L and the dI/dt in this interconnect, even accumulated,
  remain small). One challenge, though, is that the number of resistors in the extracted power nets can be in the tens to few hundreds of millions. In a later article we’ll discuss power net reduction techniques and hierarchical analysis, along with other ways to enable efficient computation of these large networks.
• Adding decoupling on-chip is an effective way to control VDD voltage variation, since the decoupling circuitry can locally store charge to be made available at times when high current transients occur. Such decoupling has traditionally used MOS transistor gate capacitance (called decaps), but as VDD voltage scales down, sub-threshold and dielectric leakages within the decaps have come to limit their number, and their placement has to be carefully chosen to maximize their desired effect while minimizing high current draw. More recently, active decoupling circuitry has been included on high-speed designs, and this suffers from fewer undesirable characteristics.

Problem Formulation

where:

• VDD’ is the voltage monitored at the source terminal of each VDD-connected PMOS device.
• VDD is the (usually fixed) externally-provided power supply voltage connected to all VDD power pads.
• IR is the resistive voltage drop, accumulated for each path from the source terminal to the power pad
• L(dI/dt) is the inductive voltage drop, similarly accumulated for each inductive component from the source terminal to the power pad

Similarly, GND’ may be derived for all GND-connected NMOS drain terminals.

Note that VDD’, I and dI/dt may be fixed, static values or time-varying, depending on the kind of analysis that we wish to perform and the data available to us.

Further, note that determining the possibly time-varying value of VDD’, and attempting to keep its variation from VDD within, say, 10%, serves merely as a gating check and not as a detailed verification of design performance. For such verification the values of VDD’ would need to be somehow backannotated to the circuit and performance verified under voltage drop conditions. This will be discussed in later articles.

For now, let’s wrap up this introductory article. The second article will discuss what data is required in order to perform voltage drop verification and analysis.

Notes

1. C4: Controlled Collapse Chip Connect, an IBM innovation in the 1960s, is a packaging technology that flips over the chip, connecting it to the external system through an array of solder balls that are remelted during final assembly.
2. The implicit definition of a power net used by many EDA tools runs something like this: a net that resistively connects together a number (user-defined, default may be hundreds to thousands) of PMOS sources or NMOS drains, and passes to a fixed or time-varying voltage source (or other VDD/GND definition) through resistors or inductors only. Blocking capacitors are clearly illegal under this definition, as are the pass transistors that may be seen in power management or voltage regulation.