|Summary: In this article we're going to introduce the concept of time into voltage drop analysis, in the form of time-varying current sources attached to the extracted power grid. With this approach it is possible to perform a crude, abstracted voltage drop analysis.|
In the previous article we reviewed static IR voltage drop, where a constant-current source is attached to some or all of the end or intermediate nodes of an extracted power net. In effect, this approach models the situation in the diagram below. Note that this diagram shows only a small subset of power net nodes have sources attached; in practice, the majority if not all of the lowest level nodes will sink current.
In this article we’re going to describe replacing the constant-current sources, annotating instead time-varying piecewise-constant current sources. The locations, or tap points, to which these sources are attached is as before, namely either at the lowest or intermediate nodes in the power net. The diagram below shows the approach this methodology takes.
Much of this article describes alternative methods of calculating the value of these piecewise-constant current sources, and the approaches used to determine the granularity in the time domain.
Calculating these abstracted time-varying currents can be done in several ways, generally falling into one of the following two most common methods:
- Vector-dependent, or simulation-driven, methods
- Vectorless methods, usually static-timing driven (the subject of tomorrow’s article)
Like all simulation-driven verification, whether RTL, gate or transistor-level, these methods are extraordinarily computationally intensive. There are methodologies that employ RTL simulation to discern discrete time periods of most significant circuit activity, and use these periods, cut out with appropriate initialization sequences, as stimulus to drive the voltage drop analysis, and these do help to reduce the burden somewhat.
Abstracting information from simulation, through SAIF or verbose VCD files, is possible, as is the option to vary the time-granularity of the current sources through averaging segments. In figure 2 above, 5 segments are shown. The compute effort could be reduced by averaging segments 1 and 2, and segments 3 and 4. The cost would be to precision. Averaging across the entire time interval would give good average currents for current-density analysis, or for static voltage drop analysis (as in figure 1 above.)
Given a switching interval (or its inverse, frequency), it is possible to calculate the current for each node, for each time interval, using the equation I = 0.5 * effective_load_capacitance * VDD^2 * effective_frequency. These are the values plugged into the index tables of the piecewise current model.
One of the most-repeated complaints about all vector-driven methods is that it is difficult to find the vector pairs or patterns that maximally draw current from the power grid, and that using user-defined patterns tends to underestimate the voltage drop and failing to identify all potential problem areas. There’s an element of truth in this argument, and I am in broad agreement with it. For gate-level circuits, a successful approach to identify such vector pairs has been developed using a multi-objective genetic algorithm (see Yi-Min Jiang’s paper in ISLPED99.) This approach, though, like all two-step approaches (which in step one compute currents and in an independent step two compute their accumulation and distribution within the power grid) abstract away some critical information. We’ll return to this in a later article, when we discuss in detail the two-step approaches and their limitations.
In the next article we’ll discuss the vectorless methods.