|Summary: As an abstract description you can consider each power distribution network to be mesh-like, of varying sparsity, with voltage sources from external to the chip connecting at some (peripheral or distributed) locations on higher level metal layers, and with transistor connections made on the lowest or contact layer, usually that immediately beneath metal1. Like all EDA tools, there's going to be a 'modeled equivalent' of the transistor. In this article we're going to introduce the simplest of all possible models, a static current, as modeled by a constant-current source.|
In the second article in this series we introduced the electrical and physical data made available for each power net. As an abstract description you can consider each power distribution network to be mesh-like, of varying sparsity, with voltage sources from external to the chip connecting at some (peripheral or distributed) locations on higher level metal layers, and with transistor connections made on the lowest or contact layer, usually that immediately beneath metal1.
The primary variation in the capability offered by voltage drop analysis tools is in what gets connected to this power distribution network. On the chip itself there will be a PMOS source at the VDD-connected contact, and an NMOS drain at the GND-connected contact, but in the voltage drop analysis tool, like all EDA tools, there’s going to be a ‘modeled equivalent’ of the transistor. In this article we’re going to introduce the simplest of all possible models, a constant-current source.
A stylized description is given in the following diagram:
The solder bumps at the top-most level connect to a coarse grid. Below this are metal layers that distribute power in various directions:
- x direction; for instance, the power route contained within each standard cell entity, connected by direct abutment to adjacent neighbors.
- y direction; for instance strapping and feed-throughs to connect power from one stick of gates to an adjacent one (perhaps interdigiated).
- both directions; for instance, power rings surrounding embedded cores and memories, with connections to the next higher and next lower levels.
Each intersection, in each layer, has a capacitor connected to ground.
In this stylized description, MOS or gate currents are modeled by a constant-current source. There are several questions designers need to consider when using this approach:
- How many will there be?
The number of current sources can be as many as the number of MOS elements attached to the power net. In the case where a large, pre-characterized IP block (core, or memory, for instance) is instantiated, it’s common to take the peak I(VDD) figure, and divide it by the number of expected taps at the power ring/core top-level to get an estimated peak current per tap. In the absence of detailed design information, user may define an expected number of taps, based on prior design experience.
- What will their value be?
There are many methods to determine the value of the constant-current source, including:
- A user-defined estimate, perhaps specified by instance name, die x,y region; or by wildcarding the instance name.
- Each MOS transistor can be analyzed, and given a user-supplied estimate of the switching frequency (again, possibly modified by die x,y region), the I(max) of the MOS can be calculated as 0.5*load_cap*frequency*VDD^2
- The I(DSAT) of each MOS can be used, modified by x,y region again.
- In the example given above, where a pre-characterized RAM or IP block is instantiated, distributing the known peak current, I(MAX) over N taps results in I(MAX)/N per tap.
- With the clock network alone constituting anywhere from 30% to 70% of a high-performance digital design’s current draw, some detailed analysis of this network, suitably back-annotated with VDD and GND can give a good first-level estimate of expected peak current.
- Where will they be located?
The taps will be located at the interface between the power net and the switching entity, typically at the contact layer. For IP blocks and RAMS the interface is, for these static currents, at the power rign of the instantiated block.
- What kind of analysis is supported?
At the taps for which current sources have been applied, the voltage VDD’ (equal to VDD - IR) has beeb calculated. This gives us the DC drop for this set of estimated currents, without inductive drop, and without the current contribution made by decoupling caps - in short, this analysis assumes all current will be coming from off-chip, through the power or ground bond pads.
This is a slightly unreal situation, and since decaps typically provide around one half of the peak current requirements, serving to increase the regulation, the computed VDD’ is not terribly precise.
So this analysis is limited to roughly checking if the VDD’ varies from nominal VDD by more than the budgetted variance (as well as a quick check of the DC current density though the power net conductors - see a future article). Performance verification under this DC drop value can be undertaken — some attempts have been made, particularly with static timing tools, to take this set of VDD’ values, back-annotate them to the circuit, and recalculate the new critical path timing value — but it gives a result of poor precision that does not necessarily approach the upper bound of variance, because there are no dynamic voltage gradients that would exist on the real chip.
Also, if all the current taps are peak values, or estimated conservatively, the VDD’ value is going to be extremely conservative.
At best this analysis, using constant-current values of varying degree of precision, can give a very rough idea of the robustness of the power net. Expected results from this analysis should be:
- Does the VDD variation meet budgetted value, within 50% or so?
- Is the DC, unidirectional current density within acceptable limits for the metallization and via designs?
- Are there any gross errors in the power net - things like disjoint net segments, where power has not been connected, or current starving to the MOS because of inordinately high power net resistance (too few vias, or conductors laid out too narrow.)
- Is there too little VDD variation? This could mean that too much metal, in tracks laid down too thick, and on too may metal layers, has been dedicated to the power net. This compromises routing resources for signal nets, and wastes metal layers. At around 5% to 10% of die cost per upper metal layer, it pays to be economical with power routing.